Technical Documents for Public Review

This is a new page where technical documents will be available for public review.

Current Documents Available for Review:

PSL / AFU Interface: CAPI 2.0 – Commenting period closes April 30, 2017

The POWER Service Layer to Accelerator Functional Unit (PSL / AFU) interface communicates to the acceleration logic running on the FPGA. Through this interface, the PSL offers services to the AFU. The services offered are cache-line oriented and allow the AFU to make buffering versus throughput trade-offs.

The interface to the AFU is composed of six independent interfaces which together allow software to control the AFU state and allow the AFU to access data in the system.

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64-Bit ELF V2 ABI Specification: Power Architecture – Commenting period closes April 30, 2017

This specification defines the OpenPOWER ELF V2 ABI (application binary interface). This ABI is derived from and represents the first major update to the Power ABI since the original release of the IBM® RS/6000® ABI. It was developed to make extensive use of new functions available in OpenPOWER-compliant processors. It expects an OpenPOWER-compliant processor to implement at least Power ISA V2.07B with all OpenPOWER Architecture instruction categories as well as OpenPOWER-defined implementation characteristics for some implementation-specific features.

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ELFv2 ABI Compliance TH/TS Specification – Commenting period closes April 30, 2017

The OpenPOWER ELFv2 Application Binary Interface (ABI) Compliance Test Harness and Test Suite (TH/TS) Specification provides the test suite requirements to demonstrate compliance with the OpenPOWER ELFv2 ABI Specification.  It describes the tests required in the test suite and a test harness needed to execute the test suite. It also describes the successful execution of the test suite, including what it means for an optional feature to fail.

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OpenPOWER Memory Bus (OPMB) Specification – Commenting period closes April 30, 2017

The OpenPOWER Memory Bus Specification defines the OpenPOWER Memory Bus Architecture.  The architecture and spec are used to develop Memory Function Units(MFU) and to integration of those MFUs into the OpenPOWER system structure. An MFU is a logic block developed by a member of the OpenPOWER eco-system to attach special purpose memory technology and function processing for data stored in the memory technology.

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