Neokylin Advanced System(Virtualization Edition) is specialized for enterprise data center, possessing functions like virtualization management, dynamic migration, high availability protection, load balance and energy-saving dispatching. It can increase data utilization, decrease energy consumption and breakdown rate, and improve manageability of application system. Therefore, Virtualization edition is the best strategic choice for users requesting lower cost, faster reward and free application model.

The Desktop Virtualization for Neokylin secure cloud operating system dedicates to solve problems in running desktop system, such as the difficulties in controling enterprise information scattered in desktop system, high cost but low efficiency of IT maintenance and high energy consumption. With virtualization, all the data was collected and stored into the clustered data center, to ensure the confidentiality, simplify the deployment and maintenance of hardware and software, and save a lot of electricity.

NeoKylin Linux Security OS is self-determination, controlled and high grade security Operating System software, which is based on LSM mechanism of SELinux subsystem framework, provides the privilege management function by Separation of the Three Powers, customized system security based on customers requirement. It provides the unified Security Management Centre(SMC), which supports security mode switching, the important data encryption storage, management of privilege users, personal Identification based two-factor certification, the least privilege of process, Type-Based Access Control with role, network safety protection, fine grain Security Auditing, delete the files in security, etc. It takes all-directional system safety protection for subscriber of government and enterprise.

NeoKylin Linux Advanced Server Operating System comes with several kernel-level features and power management capabilities that let you get the maximum performance from your systems. These features lead to greater performance for your critical workloads and processes. NeoKylin Linux Advanced Server provides management tools which easily to deploy database and middleware. It’s easy for the manager to monitor memory, storage and networking resources through Integrated monitor tool based on web in real time. NeoKylin Linux Advanced Server is a versatile platform that can be deployed on physical systems, as a guest on the major hypervisors, or in the cloud. It also includes a complete LAMP stack (Apache/Tomcat, PHP/Perl/Python, MySQL/PostgreSQL), file and print services (NFS, CIFS/SMB, CUPS), and authentication services (openldap, kerberos5).

Based on the HA software products of NeoKylin Server Software, NeoKylin HA Cluster Software, with three advantages of “reliable system”, “reliable data” and “reliable applic hardware and software systems and the stability and reliabilitation”, aims to achieve HA protection for business systems, improvesy of applications running, provides the anti-fault system to support the reliability requirements of the key business systems and provides users with efficient and reliable services.

Neokylin Linux Advanced Server Operating System V7 Update2 (NKAS V7U2) was developed by CS2C with years of Linux developing experience, NKAS V7U2 is a Chinese Linux Operating System with various functions, high security, easy management and high performances, catering to business performance, expansibility and performance requirements at the virtualization, cloud computing and big data times,. It is based on CMMI5 standard, aimed at key business and data workload and widely deployed in physical and virtualized environment, public cloud platform, private cloud as well as hybrid cloud environment.

Solution for Face Recognition and Mood Recognition running on AC922 Server with NVIDIA V100 GPUs, Operating System Red Hat Enterprise Linux 7.4, compiled using the IBM Advance Toolchain.

An applications that combines facial recognition, objects detection and computer vision with a neural network to extract useful insights.

The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It uses 14 nm technology with 17 metal layers. The POWER9 processor supports direct-attach memory. It supports a maximum symmetric multiprocessing (SMP) size of two sockets and is targeted for scale-out workloads. This user’s manual describes the POWER9 processor and provides information about the registers, facilities, initialization, and use of the POWER9 processor. This document focuses primarily on the microprocessor core and the storage subsystem.

This user’s manual describes the IBM POWER8 processor single-chip module (SCM) features, facilities, components, and use. It provides information about the POWER8 processor from a programming model point of view, and is intended to be a companion to the Power Instruction Set Architecture (ISA) documentation. This document focuses primarily on the microprocessor core and the storage subsystem. It is intended for system software and hardware developers and application programmers.

Placeholder landing page for the future workgroup note.

This document provides errata against version 1.4 of the OpenPOWER ELF v2 Application Binary Interface Specification. These errata should be considered part of said specification until such time as a newer version of the full specification is published.

This document is a Non-standard Track, Work Group Note work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. Comments, questions, etc. can be submitted to the public mailing list for the parent specification at <syssw-elfv2abi@mailinglist.openpowerfoundation.org>.

The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

This Host-Bus adapter is used to connect the ExpEther40G I/O Expansion Unit (N8141-80F, N8141-81F) to a host server vi an Ethernet. Please see the material of the I/O Expansion Unit.

The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

The goal of this project is to provide functional equivalents of the Intel MMX, SSE, and AVX intrinsic functions, that are commonly used in Linux applications, and make them (or equivalents) available for the PowerPC64LE platform.

This document is a Work Group Note work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 0.9.5.

Comments, questions, etc. can be submitted to the public mailing list for this document at <syssw-programming-guides@mailinglist.openpowerfoundation.org>.

The purpose of the OpenPOWER FSI Compliance Test Harness and Test Suite (TH/TS) Specification is to provide the test suite requirements to be able to demonstrate OpenPOWER FSI compliance. It contains the following:

• Section describing the test harness needed to execute the test suite
• Section describing the tests required to be in the test suite
• Section describing the successful execution of the test suite, including what it means for an optional feature to fail

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.  Comments, questions, etc. can be submitted to the public mailing list for this document at <openpower-fsi–thts@mailinglist.openpowerfoundation.org>.

The purpose of the OpenPOWER CAPI Accelerator Compliance – Test Specification is to provide the test suite requirements to demonstrate compliance of an OpenPOWER CAPI Accelerator solution with the OpenPOWER Power Service Layer (PSL) to Accelerator Function Unit (AFU) Interface Specification and the OpenPOWER Coherent Accelerator Interface Architecture Version 1 (CAIA V1) Specification.

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.   Comments, questions, etc. can be submitted to the public mailing list for this document at <capi_accelerator@mailinglist.openpowerfoundation.org>.

The OpenPOWER Foundation set up the OpenPOWER Ready™ program in 2016.   Within the program, developers identify products for use by members of the OpenPOWER ecosystem.    The OpenPOWER Ready mark indicates that a product should work with other OpenPOWER Ready products.  Because of this the OpenPOWER Foundation is suggesting that entities providing such products join the foundation.

The OpenPOWER Ready Definition and Criteria – V2.0 document describes the details of the program.    Since there are several types of products categorized in the document they are listed below.  Because of the differences between the categories of products the criteria varies between them.  Developers will find the categories and criteria described in the document.

OpenPOWER Ready Product Categories

• Systems
• CAPI Accelerators – Heterogeneous accelerator attached via a CAPI enabled PCIe Adapter
• Software (Operating Systems, tool chain, and applications)
• IO Adapters – storage controllers and network controllers are examples of IO Adapters
• CAPI Adapters
• OpenCAPI™ 3.0 Adapters
• System Support Components

Companies and other entities can make a strong statement about their support of the OpenPOWER technology as an alternative to other server solutions by becoming a member of the OpenPOWER Foundation membership.

This document is a Standard Track, Work Group Specification work product owned by the OpenPOWER Ready Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.  Comments, questions, etc. can be submitted to the public mailing list for this document at <opready@mailinglist.openpowerfoundation.org>.

The Advanced Accelerator Adapter Electro-Mechanical Specification defines an electro-mechanical specification for advanced accelerator adapters within the OpenPOWER eco-system supported by IBM® POWER9™.  POWER9 modules present a 25Gbps interface organized into groups of 8 bit-lanes. Innovation within the community is encouraged for systems that support accelerated computing and the accelerator adapters needed to make heterogeneous / accelerated computing solutions available to the market. 

This specification defines two accelerator approaches. The first approach is a mezzanine card attached to the system planar via two connectors. This approach is defined in Part I: Mezzanine Adapter Card.

The second approach is via cable and is defined in Cabled Interface Extension. While the accelerator card form factor is not defined in this specification Part II: Cabled Interface Extension assumes a PCIe® card for illustration.

The electrical characteristics of the 25Gbps channel are defined in Part III: 25 Gbit/sec Electrical Channel.

This document is a Standard Track, Workgroup Specification work product owned by the 25G IO Interoperability Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Document Development Guide version 1.1.0.  Comments, questions, etc. can be submitted to the public mailing list for this document at

<25giomode-p9_25gbps_phy@mailinglist.openpowerfoundation.org>.

Software solution for High Availability preventing data loss and protecting your IT system which finally leads to saving time and money.

EXPRESSCLUSTER X is supported on POWER9 and prior.

The purpose of this document is is to define a method and a template to collect Physical Science use cases from scientists and research engineers working on Physical Science projects in the context and within the scope of the OpenPOWER Foundation for Physical Science Workgroup.

An effective method that is shared by all stakeholders and participants could contribute to:

• Understanding the workflow, starting with user expectations
• Helping Physical Science projects maintain costs within a chosen envelope
• Mapping the functionalities to the scientific requirements
• Removing possible misunderstanding between the scientific community and ICT stakeholders.

This document is a Non-standard Track, Work Group Note work product owned by the OpenPower Workgroup for Physical Science.
Comments, questions, etc. can be submitted to the public mailing list for this document at
<opfps-method@mailinglist.openpowerfoundation.org>

The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

This Host-Bus adapter is used to connect the ExpEther40G I/O Expansion Unit (N8141-80F, N8141-81F) to a host server vi an Ethernet. Please see the material of the I/O Expansion Unit.

The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

The world’s first OpenPOWER enterprise class high-performance 4-socket server designed for data intensive applications with outstanding footprint.

This page under construction

Interactive, real-time editor with GUI features to facilitate the learning, usage, and implementation of parallel programming using OpenMP and OpenACC with execution on multicore processors and GPUs. Parallware Trainer enables experiential learning of parallel programming to universities, individual developers, and OpenPOWER ecosystem partners for education, academic research and application development on OpenPOWER.

This paper describes how to port various pre-built application binaries used in BWAKIT into OpenPOWER architecture and execute the BWAKIT pipeline successfully. 

Next Generation Sequencing (NGS) technology produces large volume of genome data, which gets processed using various open source Bioinformatics tools. The configuration and compilation of some of the bioinformatics tools (e.g. BWAKIT, root) are challenging, requiring application porting for some architectures (e.g. IBM Power). Moreover, the application porting should not change the semantics of the program and output generated from different architectures should be similar across different architectures. Burrows-Wheeler Aligner (BWA) is the most popular genome mapping application used in BWAKIT toolset. The BWAKIT provides pre-compiled binaries for x86_64 architecture and end-to-end solution for genome mapping.  This paper describes how to port various pre-built application binaries used in BWAKIT into OpenPOWER architecture and execute the BWAKIT pipeline successfully.  In addition, it reports the validation of the output results on OpenPOWER to confirm the successful porting of BWAKIT. 

Note:  This paper is the result of collaboration within members of the Personalized Medicine Workgroup and Sidra medical and Research Center. 

The POWER Service Layer to Accelerator Functional Unit (PSL / AFU) interface communicates to the acceleration logic running on the FPGA. Through this interface, the PSL offers services to the AFU. The services offered are cache-line oriented and allow the AFU to make buffering versus throughput trade-offs.

The interface to the AFU is composed of six independent interfaces:
• AFU Command Interface is the interface through which the AFU sends service requests to the PSL.
• AFU Buffer Interface is the interface through which the PSL moves data to and from the AFU.
• PSL Response Interface is the interface through which the PSL reports status about service requests.
• AFU MMIO Interface is the interface through which software reads and writes can access registers within the AFU.
• AFU Control Interface allows the PSL job management functions to control the state of the AFU.
• AFU DMA Interface allows the AFU to send native PCIe Writes and Reads and to receive Read Completion data.

Together these interfaces allow software to control the AFU state and allow the AFU to access data in the system.

This document is a Standard Track, Work Group Specification work product owned by the Accelerator Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0. Comments, questions, etc. can be submitted to the public mailing list for this document at
<aclwg-afu_psl@mailinglist.openpowerfoundation.org>.

The OpenPOWER Memory Bus Specification defines the OpenPOWER Memory Bus Architecture.  The architecture and spec are used to develop Memory Function Units(MFU) and to integration of those MFUs into the OpenPOWER system structure. An MFU is a logic block developed by a member of the OpenPOWER eco-system to attach special purpose memory technology and function processing for data stored in the memory technology.  An example of MFU might be a database function accelerator which attaches dense flash memory technology.  This figure illustrates the concept.

Comments regarding the specification content and suggestions for updates may be submitted to the following mailing list:

<memwg-opmb@mailinglist.openpowerfoundation.org>

The MegaRAID® SAS 9380-8i8e, with eight internal and eight external ports
in a low-profile form factor, delivers two 1.2 GHz PowerPC processor cores
and a 72-bit DDR3 interface that drives 2 GB cache memory. Powered by
the SAS3316 dual-core ROC, with 16 native SAS/SATA ports, the 9380- 8i8e
controller can take full advantage of the latest PCI Express 3.0 interface
to provide higher performance and increased throughput. The 12 Gb/s
MegaRAID SAS 9380-8i8e is designed to direct connect eight drives
inside the box or eight drives outside the box. By leveraging SAS expander
technology, users can expand to up to 240 drives increasing inside the box
drive count or through supporting external JBOD storage enclosures.

The MegaRAID® SAS 9361-24i, with twenty-four internal ports in a lowprofile*
form factor, delivers two 1.2 GHz PowerPC processor cores and a
72-bit DDR3 interface that drives 4 GB cache memory. Powered by the
SAS3324 dual-core ROC, with 24 native SAS/SATA ports, the 9361-24i
controller can take full advantage of the latest PCI Express 3.0 interface
to provide higher performance and increased throughput. The 12 Gb/s
MegaRAID SAS 9361-24i is designed for configuring high-density storage
servers with up to 24 drives via direct connection inside the box or up to
240 drives by leveraging SAS expander technology.

The Avago MegaRAID® SAS 9361-16i, with sixteen internal ports in a lowprofile
form factor, delivers two 1.2GHz PowerPC processor cores and a
72-bit DDR3 interface that drives 2GB cache memory. Powered by the
SAS3316 dual-core ROC, with 16 native SAS/SATA ports, the 9361-16i
controller can take full advantage of the latest PCI Express 3.0 interface
to provide higher performance and increased throughput. The 12Gb/s
MegaRAID SAS 9361-16i is designed for confi guring high-density storage
servers with up to 16 drives via direct connection inside the box or up to
240 drives by leveraging SAS expander technology.

The OpenPOWER ELFv2 Application Binary Interface (ABI) Compliance Test Harness and Test Suite (TH/TS) Specification provides the test suite requirements to demonstrate compliance with the OpenPOWER ELFv2 ABI Specification.  It describes the tests required in the test suite and a test harness needed to execute the test suite. It also describes the successful execution of the test suite, including what it means for an optional feature to fail.

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0.

Comments, questions, etc. can be submitted to the public mailing list for this document at
<openpower-elfv2abi-thts@mailinglist.openpowerfoundation.org>.

HGST Ultrastar He8 SATA 8TB 3.5-inch Helium Platform Enterprise Hard Disk Drive

SATA 6Gb/s and SAS 12Gb/s

12Gb/s SAS compatible with next gen data centers; backwards compatible with 6Gb/s SAS

2.5M hours MTBF 2 rating & 5-year limited warranty

Instant Secure Erase (ISE) & Self-Encrypting Drive (SED) options

Advanced format 4Kn and 512e models

HGST Ultrastar® 7K6000 SATA 6TB 3.5-inch Enterprise 7200 RPM Hard Disk Drive

128MB cache buffer improves response time and data management

Instant Secure Erase (ISE) & Self-Encrypting Drive (SED) options

Advanced format 4Kn and 512e models up to 6TB; 512n format available in 4TB and 2TB capacities

2M hours MTBF 2 rating & 5-year limited warranty

This specification defines the OpenPOWER ELF V2 ABI (application binary interface). This ABI is derived from and represents the first major update to the Power ABI since the original release of the IBM® RS/6000® ABI. It was developed to make extensive use of new functions available in OpenPOWER-compliant processors. It expects an OpenPOWER-compliant processor to implement at least Power ISA V2.07B with all OpenPOWER Architecture instruction categories as well as OpenPOWER-defined implementation characteristics for some implementation-specific features.

The Executable and Linking Format (ELF) defines a linking interface for executables and shared objects in two parts: the first part is the generic System V ABI, the second part is a processor-specific supplement.  This document, the OpenPOWER ABI for Linux Supplement for the Power Architecture 64-bit ELF V2 ABI, is the OpenPOWER-compliant processor-specific supplement for use with ELF V2 on 64-bit IBM Power Architecture® systems. This is not a complete System V ABI supplement because it does not define any library interfaces. This document establishes both big-endian and little-endian application binary interfaces. OpenPOWER-compliant processors in the 64-bit Power Architecture can execute in either big-endian or little-endian mode. Executables and executable-generated data (in general) that subscribes to either byte ordering is not portable to a system running in the other mode. 

ERRATA:

An OpenPOWER ELFv2 Errata: For ELFv2 ABI Version 1.4 has been published.  These errata should be considered part of this specification until such time as a newer version of the full specification is published.

This document is a Standards Track, Work Group work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.

Comments, questions, etc. can be submitted to the public mailing list for this document at

<syssw-elfv2abi@mailinglist.openpowerfoundation.org>.

Data center, cloud and high-performance computing environments not only require large amounts of storage capacity, they also must provide the data protection and performance today’s applications and end users demand. The MegaRAID SAS 9361-16i 12Gb/s RAID controller card addresses these needs by delivering proven performance and RAID data protection for a range of server storage applications.

Connect up to 16 SATA or SAS drives via direct connection inside the box or up to 240 drives leveraging SAS expander technology
Fit into rack-mounted servers with low-profile form factor and side-mounted SAS connectors
Support critical, high-bandwidth applications with PCIe® 3.0 connectivity
Balance protection and performance for critical applications with RAID levels 0, 1, 5, 6, 10, 50, and 60
Add more protection and peace of mind with optional CacheVault® flash cache protection.

2 Terabyte CAPI 1.0 enabled Flash Storage Card
Includes support for CAPI SNAP Near Storage Acceleration
Utilizes 2x onboard M.2 22110 NVMe SSDs

OpenPOWER Ready™ is a mark used by the OpenPOWER Foundation to enable OpenPOWER ecosystem product developers to indicate that a product has been shown / demonstrated to meet a minimum set of characteristics and should be interoperable with other OpenPOWER Ready products.  A signed Trademark License Agreement (TMLA) is required for a product to display the mark.   Use of the trademark and the trademark is governed by the TMLA Usage Guidelines. 

The OpenPOWER Foundation documentation template provides a framework for OpenPOWER public and private documentation. The goal of the template and this writeup is to promote community contributions to OpenPOWER documenation and to enable new contributions within a common look and feel.

The major sections of this document addresses the following topics:

• Getting started: This section details tools and commands used to contribute to OpenPOWER documentation. All users who are new to OpenPOWER Foundation documentation should start here.
• Creating a new document: This section provides step-by-step instructions on how to create a new document from scratch. Use this section to start a new document.
• Modifying an existing document: This section highlights common steps in editing an existing OpenPOWER Foundation document. Use this section as a guideline for contributing to an existing document.
• Debugging build failures: This section provides examples of the two most common types of build failures and helps users find the relevant failure information.
• Publishing OpenPOWER Documents: This section explains key document types and the appropriate work flow for publishing OpenPOWER Foundation documents.
• Understanding the project structure: This section provides detailed descriptions of the various project components and their roles in the documentation creation process.
• Policies and conventions: This section contains the generally accepted guidelines for creating OpenPOWER documentation. Use this section as a reference for documentation style beyond template provided features.
• Frequently asked questions: This section answers common questions. Use this section when the other sections do not answer your questions.
• Common git commands: This section contains examples of commonly used git commands. Reference this section to find information on a specific git operation.
• Finding more information: This section provides pointers to on-line information about XML, Docbook, Maven, and other relevant references.

Power ISA™ Version 3.0B

The Power Instruction Set Architecture (ISA) Version 3.0B is a specification that describes the architecture used for the IBM POWER9 processor.  It defines the instructions the processors execute.  It is comprised of three books and a set of appendices.

• – Book I, Power ISA User Instruction Set Architecture, covers the base instruction set and related facilities available to the application programmer.
• – Book II, Power ISA Virtual Environment Architecture, defines the storage model and related instructions and facilities available to the application programmer.
• – Book III, Power ISA Operating Environment Architecture, defines the supervisor instructions and related facilities.

The OpenPOWER ISA Compliance Definition defines the test suite requirements to demonstrate OpenPOWER ISA Profile compliance.

It contains the following:
• Section describing the test harness needed to execute the test suite
• Section describing the tests required to be in the test suite
• Section describing the successful execution of the test suite, including what it means for an optional feature to fail.

The initial version of this document will be based on the POWER8 systems. It is expected that this
document shall be updated for future generation OpenPOWER systems.

The input to this specification are the following specifications:

1. OpenPOWER Specification: Power Instruction Set Architecture (ISA) – OpenPOWER Profile which describes the categories of the POWER ISA Version 2.07 B that are required in the OpenPOWER processor chip architecture.
2. IBM Power ISA Version 2.07 B

The testing of a processor implementation’s compliance against the Power ISA – OpenPOWER Profile is ultimately intended to ensure that software shown to execute properly on one compliant processor implementation will execute properly on a different also compliant processor implementation. The testing is not intended to show that the processor implementation under test is robust under all possible operating conditions, inputs, or event time interactions. It is intend to show that the processor implementation under test implemented the ISA as specified and that the ISA specification was interpreted by the processor developers as intended by the ISA specification author.

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. 

Comments, questions, etc. can be submitted to the public mailing list for this document at
<openpower-isa-thts@mailinglist.openpowerfoundation.org>.

The OpenPOWER CAPI Accelerator Compliance – Test Specification provides the requirements for a test suite to demonstrate the compliance of an OpenPOWER CAPI Accelerator solution with the relevant OpenPOWER specifications. The OpenPOWER specifications covered are:

1. OpenPOWER Power Service Layer (PSL) to Accelerator Function Unit (AFU) Interface Specification which describes the hardware level interface between the PSL and the AFU.  It is used by AFU developers to easily connect a specialized accelerator into the OpenPOWER system structure.
2. OpenPOWER Coherent Accelerator Interface Architecture Version 1 (CAIA V1) Specification   which describes the software interface to the PSL and is used by accelerated application developers.

The OpenPOWER CAPI Accelerator Compliance – Test Specification document is a Standards Track, Work Group Specification owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.

Comments about this document may be submitted to the Compliance Workgroup by emailing to <capi_accelerator@mailinglist.openpowerfoundation.org>.

Eight-port internal 12Gb dual core ROC-based SAS solution for data center, cloud, and performance applications using up to 128 SAS or SATA devices

ConnectX®-4 Lx EN network interface card, 25GbE dual-port SFP+, PCIe3.0 x8, tall bracket, ROHS R6

ConnectX®-4 EN network interface card, 100GbE, dual-port QSFP28, PCIe3.0 x16, tall bracket, ROHS R6

ConnectX®-3 Pro EN network interface card, 10GbE, dual-port SFP+, PCIe3.0 x8 8GT/s, tall bracket, RoHS R6

ConnectX®-3 EN network interface card, 40/56GbE, dual-port QSFP+, PCIe3.0 x8 8GT/s, tall bracket, RoHS R6

ConnectX®-4 Lx EN network interface card, 10GbE dual-port SFP+, PCIe3.0 x8, tall bracket, ROHS R6

Spectrum(TM) based 40GbE, 1U Open Ethernet Switch with MLNX-OS, 16 QSFP28 ports, 2 Power Supplies (AC), short depth, Rangeley CPU, P2C airflow, Rail Kit must be purchased separately, RoHS6

Spectrum(TM) based 10GbE/100GbE 1U Open Ethernet switch with MLNX-OS, 48 SFP28 ports, 8 QSFP28 ports, 2 power supplies (AC), x86 dual core, Short depth, P2C airflow, Rail Kit, RoHS6

CAPI enabled hardware compression

Broadcom NetXtreme® C-Series Dual Port 25G Cloud-Optimized PCIe Ethernet NIC

This document describes a Field replaceable unit Support Interface(FSI) suited to service all chips in a computer system via a common serial interface. Key features are ease of use, easy scalability, robustness, and support for virtualization and the tunneling of interrupts and DMA control signals across the interface. FSI is superior to similar industry standard interfaces in these and many other features including speed, distance, data protection, and address range.

FSI is a point to point two wire interface operating in half duplex mode, which is capable of supporting distances of up to 4 meters at up to 166 MHz bus frequency. All operations are fully CRC checked to allow error recovery.
With its versatile architecture, the FSI is suited for a wide range of applications from service access to in-system test.

Power8 2-socket server system – Open Compute, Open Rack form factor, based upon OCP Barreleye G1 specification.

High-density, scalable, and cost-effective design includes 60 Ultrastar® 3.5-inch drive modules in a 4U storage enclosure and offers 2x2x4-lane SAS 12Gb/s performance, high availability (HA), and hot-swappable components.

IBM Power ISA™ Version 2.07 B

The Power Instruction Set Architecture (ISA) Version 2.07 B is a specification that describes the architecture used for the  IBM® POWER8®, IBM® POWER8® with NVIDIA® NVLink™ Technology, the Suzhou Powercore Technology CP1 processor & prior IBM Power Architecture® processors.  It defines the instructions the processors execute. It consists of five books and a set of appendices.

• Book I, Power ISA User Instruction Set Architecture, covers the base instruction set and related facilities available to the application programmer.
• Book II, Power ISA Virtual Environment Architecture, defines the storage model and related instructions and facilities available to the application programmer.
• Book III-S, Power ISA Operating Environment Architecture – Server Environment, defines the supervisor instructions and related facilities used for general purpose implementations.
• Book III-E, Power ISA Operating Environment Architecture – Embedded Environment, defines the supervisor instructions and related facilities used for embedded implementations.
• Book VLE, Power ISA Operating Environment Architecture – Variable Length Encoding (VLE) Instructions Architecture, defines alternative instruction encoding and definitions intended to increase instruction density for very low end implementations.

The Power ISA specification is an important resource for software developers especially compiler and tool chain developers.  Firmware and operating system developers will also find it essential.  The reference link will require an IBMid to access.  If you do not have one please request one as you login.

2U 2S Power8 Storage Rich Server

SwitchX®-2 based 48x10Gb and 12x40Gb, 1U Open Ethernet Switch with MLNX-OS

Spectrum® based 100GbE, 1U Open Ethernet Switch, 32 QSFP28 ports

SwitchX®-2 based 10GbE/40GbE, 1U

Open Ethernet Switch with MLNX-OS, 12

QSFP+ ports

Set of open source development tools and runtime libraries which allows users to take leading edge advantage of IBM’s latest POWER hardware features on Linux

AuvizDNN is an optimized library of functions similar to CuDNN to create deep learning algorithms on FPGA accelerators.

The purpose of this document is to define the architecture and minimum system requirements on which all LoPAPR platforms are based. These requirements are intended to be precise enough to assure OS compatibility for several operating system (OS) levels (current and “n-1” versions), broad enough to cover workstations through server platforms in single or multiprocessor configurations, and forward-looking enough to allow evolution.

Emulex Gen 6 (16Gb) Fibre Channel HBA

Emulex Gen 5 (16Gb) Fibre Channel HBA

Emulex 8Gb Fibre Channel HBA

Emulex 8Gb Fibre Channel HBA

Emulex Gen 6 (32Gb) Fibre Channel HBA

Quad-port 8Gbps Fibre Channel Adapter, low profile, PCIe® 2.0 x8

The PBlaze4 Series is Memblazes’ next generation enterprise SSD designed to deliver consistent level of performance and  reliability for the most demanding data center applications, including database, CDN, Tier1 Caching, Virtualization and Cloud Computing.

Compiler for Fortran on Linux LE on Power systems

Compiler for C and C++ on Linux LE on Power systems Free of charge

Compiler for C and C++ on Linux LE on Power systems

OpenPower8 based 2-Socket Rack Server

Ubuntu Leading OS for Cloud & Scaleout computing

The DRAGEN Bio-IT Platform is based on the highly reconfigurable DRAGEN Bio-IT Processor which is integrated on a PCIe card and is available in a pre-configured server that can be seamlessly integrated into customer’s NGS bioinformatics workflows. The platform can be loaded with highly optimized algorithms for many different NGS secondary analysis pipelines such as Whole Genome or Exome, RNAseq, Methylome, Microbiome and Cancer.

Connect-IB® Host Channel Adapter, dual-port QSFP, FDR 56Gb/s, PCIe3.0 x16, tall bracket, RoHS R6

ConnectX®-4 VPI adapter card, EDR IB (100Gb/s) and 100GbE, single port QSFP28, PCIe3.0 x16, tall bracket, ROHS R6

ConnectX®-4 Adapter Card

NVIDIA-K80-GPU PCIe gen3 x16 GPU Adapter (FC EC4B; CCIN 2CE9)

NVIDIA® K40 GPU Adapter. PCIe gen3 x16 GPU Adapter (FC EC47; CCIN 2CE8)

The Emulex® PCIe G3 x8 4×10 4-Port Ethernet SR Optical / SFP+ Cu. This adapter uses Emulex
controller XE201 (in NIC only mode)

The QLogic® 57810 PCIe2 4-Port (2P 10Gb+2P 1GbE) SR/SFP+ Cu +RJ45 Adapter

The QLogic® 57810 PCIe2 2-port 10GBaseT RJ45 Adapter

The Broadcom® NetXtreme® BCM 5719 PCIe2 4-port 1GbE Adapter

The Emulex® PCIe Gen3 4-port (10Gb FCoE and 1GbE) SR&RJ4 – SR and Cu. This adapter uses
Emulex Engine™ XE201 (in NIC+ FCoE converged NIC mode)

The Mellanox® ConnectX-3® Pro PCIe3 2-Port 10 GbE NIC RoCE SR/SFP+ adapter

The Mellanox® ConnectX-3® PCIe3 2-Port 40 GbE NIC RoCE QSFP+ Adapter

The Mellanox ConnectX®-4 PCIe3 1-port 100Gb EDR IB Adapter x16

The Mellanox ConnectX®-4 PCIe3 2-port 100Gb EDR IB Adapter x16

Dual-port Gen 5 (16Gbps) Fibre Channel Adapter, low profile, PCIe® 3.0 x4

PCIe 2.0 x8 to 8-port SAS/SATA 6 Gbps RAID-On-Chip processor

PCIe 2.0 x8 to 4-port SAS/SATA 6 Gbps RAID-On-Chip processor

PCIe 3.0 x8 to 8-Port 12 Gbps SAS/6 Gbps SATA I/O Controller

PCIe 3.0 x8 to 16-Port 6 Gbps SATA I/O Controller

One-lane PCIe 2.0 to Four-port 6Gbps SATA I/O controller

PCIe 3.0 x8 to 16-Port 12 Gbps SAS/6 Gbps SATA I/O Controller

Two-lane PCIe 2.0 to Four-port 6Gbps SATA I/O controller

PCIe 2.0 x2 to 4-port SATA 6 Gbps RAID controller

PCIe 2.0 x8 to 8-port SAS/SATA 6 Gbps I/O controller

PCIe 2.0 x4 to 4-port SAS/SATA 6 Gbps I/O controller

Dual-port 8Gbps Fibre Channel Adapter, low profile, PCIe® 2.0 x4

The Mellanox Connect-IB® PCIe3 2-port 56Gb FDR IB Adapter x16.

POWER8 Server

POWER8 Server

POWER8 Server

POWER8 Server

POWER8 Server

2205-L2C, 2205-L2G

2200-L2C, 2200-L2G

Xilinx Virtex-7 FPGA accelerator Board

Chelsio’s T520-SO-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 10 GbE memory free Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

Chelsio’s T520-BT is built upon the Terminator 5 (T5) High Performance ASIC and is a 10GBase-T 10 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

Chelsio’s T520-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 10 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

Chelsio’s T580-SO-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 40 GbE memory free Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

Chelsio’s T580-LP-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 40 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

Chelsio’s T580-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 40 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

Xilinx UltraScale FPGA accelerator Board

FPGA CAPI Accelerator Card

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

6Gb/s SAS/SATA

8 Port Configuration: 2 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

6Gb/s SAS/SATA

16 Port Configuration: 4 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller (Entry-RAID Only)

6Gb/s SAS/SATA

16 Port Configuration: 4 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

Half Length, Full Height

RAID Controller

6Gb/s SAS/SATA

24 Port Configuration: 4 internal mini SAS HD x4 ports, 2 external mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

Half Length, Full Height

RAID Controller

6Gb/s SAS/SATA

24 Port Configuration: 6 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

6Gb/s SAS/SATA

24 Port Configuration: 2 internal mini SAS HD x4 ports, 4 external mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

12Gb/s SAS and 6Gb/s SATA

4 Port Configuration: 1 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

12Gb/s SAS and 6Gb/s SATA

8 Port Configuration: 2 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

12Gb/s SAS and 6Gb/s SATA

16 Port Configuration: 2 internal mini SAS HD x4 ports, 2 external mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller; Embedded Flash Backup and AFM-700 included

12Gb/s SAS and 6Gb/s SATA

16 Port Configuration: 4 internal mini SAS HD x4 ports

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

PCIe Gen 3.0 x8

MD2 Low Profile

NVM Express NVRAM Drive

Flash-based Backup Unit: SCM-F35 Bulk

Memory Configuration: 4GB Capacity

PCIe Gen 3.0 x8

MD2 Low Profile

NVM Express NVRAM Drive

Flash-based Backup Unit: SCM-F70 Bulk

Memory Configuration: 8GB Capacity

PCIe Gen 3.0 x8

MD2 Low Profile

NVM Express NVRAM Drive

Flash-based Backup Unit: SCM-F100 Bulk

Memory Configuration: 16GB Capacity

Power8 2U2S System

This IBM® Redbooks® publication focuses on gathering the correct technical information, and laying out simple guidance for optimizing code performance on IBM POWER8® processor-based systems. There is straightforward performance optimization that can be performed with a minimum of effort and without extensive previous experience or in-depth knowledge.

IBM® and Linux® deliver servers, software, and solutions built on the IBM Power Systems™ platform. IBM’s Power servers run industry standard Linux from Red Hat®, SUSE™ and Canonical’s Ubuntu®.  This community is your source for technical resources for Linux software on Power systems, including direct access to other Linux on Power users, and the development team behind both Linux and Power technologies.

The IBM Software Development Kit for Linux on Power (SDK) is a free, Eclipse-based Integrated Development Environment (IDE). The SDK integrates C/C++ source development with the Advance Toolchain, Post-Link Optimization, and classic Linux performance analysis tools, including Oprofile, Perf and Valgrind.

The IBM® Power Systems™ information describes the IBM Power Systems servers. IBM Power Systems is the name of the family of servers based on POWER® processors.

In most cases, porting Linux applications from the x86 platform to Linux on Power is simple because both platforms are based on a common Linux version from Novell SUSE or Red Hat. Porting often requires only a GNU Compiler Collection (GCC) recompile with minor changes to some compiler and linker switches.

The NVIDIA® CUDA® Toolkit provides a comprehensive development environment for C and C++ developers building GPU-accelerated applications. The CUDA Toolkit includes a compiler for NVIDIA GPUs, math libraries, and tools for debugging and optimizing the performance of your applications. You’ll also find programming guides, user manuals, API reference, and other documentation to help you get started quickly accelerating your application with GPUs.

IBM Innovation Center teams can help you architect and enable your application on IBM Systems and software. IBM technical experts are ready to help you with your development objectives. Once you engage with our centers, you have access to IBM IT architects and specialists around the world.

BM’s CAPI technology provides a high-performance, coherent processor attach for computation-heavy algorithms on an FPGA. This innovation removes the overhead and complexity of the I/O subsystem, allowing an accelerator to operate as part of an application with a smaller programming investment.  The CAPI Developer Kit is now available through OpenPOWER member Nallatech. Nallatech provides the CAPI FPGA Card, documentation, software, and support required to implement a CAPI solution.

For the CAPI Developer Kit, see: www.nallatech.com/capi
For information on CAPI, see: http://www-304.ibm.com/webapp/set2/sas/f/capi/home.html

The Usage Guidelines outline the authorized uses of OpenPOWER Foundation’s trademarks and logos.  A signed Trademark License Agreement (TMLA) is required to display the OpenPOWER Ready mark(s) as described in the Guidelines.  The TMLA document may be downloaded from OpenPOWER Ready Trademark Agreement.

The OpenPOWER Foundation set up the OpenPOWER Ready™ program in 2016.   Within the program, developers identify products for use by members of the OpenPOWER ecosystem.    The OpenPOWER Ready mark indicates that a product should work with other OpenPOWER Ready products.  Because of this the OpenPOWER Foundation is suggesting that entities providing such products join the foundation.

The OpenPOWER Ready Definition and Criteria document describes the details of the program.    Since there are several types of products categorized in the document they are listed below.  Because of the differences between the categories of products the criteria varies between them.  Developers will find the categories and criteria described in the document.

OpenPOWER Ready Product Categories

• IO Adapters – storage controllers and network controllers are examples of IO Adapters
• Systems
• CAPI Accelerators – Heterogeneous accelerator attached via a CAPI enabled PCIe Adapter
• Operating Systems
• Applications
• System Support Components

Companies and other entities can make a strong statement about their support of the OpenPOWER technology as an alternative to other server solutions by becoming a member of the OpenPOWER Foundation membership.

Interested readers can find information about the OpenPOWER Foundation at the foundation’s website:  https://openpowerfoundation.org/.

OpenPOWER Ready™ is a mark used by the OpenPOWER Foundation to enable OpenPOWER ecosystem product developers to indicate that a product has been shown / demonstrated to meet a minimum set of characteristics and should be interoperable with other OpenPOWER Ready products.  This document is a template for submitting a request to the OpenPOWER Foundation.  Users should fill out this template and submit the request per the OpenPOWER Ready Definition and Criteria.

1U single-socket OpenPOWER platform supports up to 1,024GB memory

2U single-socket OpenPOWER platform supports up to 1,024GB memory

Ultrastar SN150 Series NVMe PCIe 3.0 x4 Half-Height, Half-Length Card Solid-State Drive (SSD)

High Density, Ultrastar SN150, PCIe SSD, 1.6TB, solid-state drives

With 4 years of development and 420,000 lines of code, the Hostboot firmware has been released! Hosted on Github along side Opal (PowerKVM), developers will find the tools and documentation to rebuild the code and bolt on enhancements. Hostboot firmware performs all processor, bus, and memory initialization within POWER® based systems and booting the POWER8 Reference Board to Linux. It prepares the hardware to load and run an appropriate payload and provides runtime services to the payload. The team specifically designed a data driven, easily configurable code stack that will enable OpenPOWER members to design systems around the P8 processor. The firmware teams will be keeping the project very active with new features to follow soon. Join the community and conversation! Github – OpenPOWER

Little Endian Linux supporting the 64bit PowerISA is a foundational part of the OpenPOWER System software stack and supports the development of OpenPOWER applications including future applications leveraging NVIDIA GPUs. The development community will now benefit from the creation of an open source software community for the development of a new ppc64el port, a Debian GNU/Linux distribution. To view additional information about this porting effort including how to access the repository of binaries and pre-installed images, visit Debian-ppc mailing list on the Debian wiki. To report bugs or other issues related to the Debian ppc64el tool as work begins in this community, developers are encouraged to join the debian-ppc mailing list or use the Debian bug reporting site at Debian bug reporting site.

xCAT offers open source system management for HPC clusters, RenderFarms, Grids, WebFarms, Online Gaming Infrastructure, Clouds, and Datacenters. It is agile, extensible, and based on years of system administration best practices and experience. Now, xCAT enables you to discover OpenPOWER nodes, management OpenPOWER HW and deploy bare-metal and VMs on the OpenPOWER nodes. xCAT is an Open Source product ready for OpenPOWER.

DESCRIPTION

The Coherent Accelerator Processor Interface (CAPI) on IBM POWER8 systems is a new means for solution architects to gain system-level performance. CAPI connects a custom acceleration engine to the coherent fabric of the POWER8 chip. The hybrid solution has a simple programming paradigm while delivering performance well beyond today’s I/O attached acceleration engines.

The CAPI Developers Community is intended to enable CAPI Developer Kit users to collaborate with other users on usage, issues, questions & to innovate.

This OpenPOWER Development Platform Workgroup Note provides the material used for the design of the Tyan SP010 development system as a reference for developers of OpenPOWER systems based on the IBM Power8TM chipset.

POWER8 Evaluation System is single socket ATX form factor, BMC based evaluation board. It is designed and will be fulfilled by Tyan Corporation an OpenPOWER Foundation Platinum member. Note that this is an early development system for “Evaluation Purposes Only” and not intended for production use. If you are interested in one or more of these Evaluation systems or boards, please click on the link below.

Attention OpenPOWER and Open Source developers – Can’t wait for Ubuntu to be generally available on POWER? Site Ox, an IBM MSP Partner, is offering Ubuntu 14.04 on Power (1 CPU, 2GB memory and 20GB disk) for $2 a day and is having a 2-week free promotion. Visit Siteox.com.

OVH offers POWER8-based public cloud computing in its RunAbove cloud. POWER8 instances, ideal for high performance computing and Big Data, are available in two flavors. The “S” flavor provides a virtual server provisioned in a shared POWER8 physical host and is suitable for development and test environments. The “2XL” flavor provides a virtual server provisioned on a dedicated POWER8 physical host and is ideal for computational-intensive workloads.

To learn more about the RunAbove POWER8 compute offerings and start experiencing how POWER8 can accelerate your Big Data projects, visit: http://labs.runabove.com/power8.

Quad-port Gen 6 (32Gbps) Fibre Channel Adapter, full-height, PCIe® 3.0 x16

Dual-port Gen 6 (32Gbps) Fibre Channel Adapter, low profile, PCIe® 3.0 x8

Quad-port Enhanced Gen 5 (16Gbps) Fibre Channel adapter, full-height, PCIe® 3.0 x8

Dual-port Enhanced Gen 5 (16Gbps) Fibre Channel Adapter, low profile, PCIe® 3.0 x8

SuperVessel is a joint effort built by IBM Research-China and IBM China Systems and Technology Development Center.  It is an open cloud platform based on POWER/OpenPOWER and OpenStack technology.  SuperVessel provides cloud services to universities, individual developers, and POWER/OpenPOWER ecosystem partners for education, academic research and application development on POWER/OpenPOWER.  There are many advanced services on SuperVessel such as Cognitive services, Big Data (Spark, Hadoop) services, Science Computing Environment, Java/Python Application Development Environment, and more.

The purpose of the OpenPOWER Instruction Set Architecture (ISA) Profile specification is to describe the categories of the POWER ISA Version 2.07 B that are required in the OpenPOWER processor chip architecture.

The purpose of the I/O Design Architecture, version 2 (IODA2) specification is to describe the chip architecture for key aspects of PCIe® based host bridge (PHB) designs for IBM® POWER8TM systems.

This document defines the Coherent Accelerator Interface Architecture (CAIA) for the IBM® POWER8® systems. The information contained in this document allows various CAIA-compliant accelerator implementations to meet the needs of a wide variety of systems and applications. Compatibility with the CAIA allows applications and system software to migrate from one implementation to another with minor changes.

The purpose of the OpenPOWER Architecture Compliance Definition document is to give a consistent approach to compliance under the guidance of the Compliance Work Group. It contains the following:
• Document the OpenPOWER specifications that contain the interfaces that are required to be OpenPOWER compliant
• Document an overview of the Compliance Test Harness and Test Suite Specifications that will be developed in Compliance sub-committees, and an outline of the contents expected in each specification
• Document procedures on how to measure and document compliance and where to submit the report for compliance

A CAPI based accelerator interfaces to the POWER system through a logic unit called the Power Service Layer (PSL).  The Accelerator Function Unit (AFU) contains the logic that implements the unique acceleration function.  This OpenPOWER Accelerator Workgroup Specification defines the logical interface between the PSL and the AFU.