Resource Catalog

This document provides requirements for a compiler to demonstrate compliance with the Power Vector Intrinsics Programming Reference, version 1.0.

This document is a Standard Track, Workgroup Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. Comments, questions, etc. can be submitted to the public mailing list for the parent specification at
<[email protected]>.

The input to this specification is the following specification which describes the vector intrinsics expected to be provided by compilers targeting PowerISA 2.07 and 3.0B or later, as implemented on POWER8 and POWER9 systems.

Power Vector Intrinsics Programming Reference (PVIPR) which is published on the resource catalog: https://openpowerfoundation.org/?resource_lib=power-vector-intrinsic-programming-reference

The PVIPR document is organized into the following chapters:
1. Introduction to Vector Programming on Power
2. The Power Bi-Endian Vector Programming Model
3. Vector Programming Techniques
4. Vector Intrinsic Reference
5. Instruction/Intrinsic Cross-Reference

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This is the first public review draft of the 64-bit ELF V2 ABI Specification, a document created and maintained and approved by the System Software Workgroup for publication.

The ABI (application binary interface) specification provides the definitions for the machine interface and inter-object interfaces for the little-endian POWER architecture.

This specification defines the OpenPOWER ELF V2 ABI which is derived from and represents the first major update to the Power ABI since the original release of the IBM® RS/6000® ABI. It was developed to make extensive use of new functions available in OpenPOWER-compliant processors. It expects an OpenPOWER-compliant processor to implement at least Power ISA V2.07B with all OpenPOWER Architecture instruction categories as well as OpenPOWER-defined implementation characteristics for some implementation-specific features.

The Executable and Linking Format (ELF) defines a linking interface for executables and shared objects in two parts: the first part is the generic System V ABI, the second part is a processor-specific supplement.  This document, the OpenPOWER ABI for Linux Supplement for the Power Architecture 64-bit ELF V2 ABI, is the OpenPOWER-compliant processor-specific supplement for use with ELF V2 on 64-bit IBM Power Architecture® systems. This is not a complete System V ABI supplement because it does not define any library interfaces. This document establishes both big-endian and little-endian application binary interfaces. OpenPOWER-compliant processors in the 64-bit Power Architecture can execute in either big-endian or little-endian mode. Executables and executable-generated data (in general) that subscribes to either byte ordering is not portable to a system running in the other mode.

SUMMARY:

The Executable and Linking Format (ELF) defines a linking interface for executables and shared objects in two parts: the first part is the generic System V ABI, the second part is a processor-specific supplement.

This document, the OpenPOWER ABI for Linux Supplement for the Power Architecture 64-bit ELF V2 ABI, is the OpenPOWER-compliant processor-specific supplement for use with ELF V2 on 64-bit IBM Power Architecture® systems. This is not a complete System V ABI supplement because it does not define any library interfaces.

This document establishes both big-endian and little-endian application binary interfaces. OpenPOWER-compliant processors in the 64-bit Power Architecture can execute in either big-endian or little-endian mode. Executables and executable-generated data (in general) that subscribes to either byte ordering is not portable to a system running in the other mode.

ERRATA:

This document is an update to version 1.4 at this link https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture and includes the following changes from Revision 1.4:

• Errata recorded at https://openpowerfoundation.org/?resource_lib=openpower-elfv2-errata-elfv2-abi-version-1-4  have been incorporated into this document.

• PowerISA version 3.1 introduces PC-relative instructions for accessing code and data. Thus compilers and assembly programmers that target version 3.1 or later can, if desired, avoid usage of a TOC pointer for such accesses. The ABI has been updated to describe the implications of this new capability.

• Appendix A, “Predefined Functions for Vector Programming,” and most of Chapter 6, “Vector Programming Interfaces,” have been removed from this document. This material is now incorpo-rated into the POWER Vector Intrinsics Programming Reference. See Section 1.1, “ReferenceDocumentation” [1] for a link to this document.

FEEDBACK:

This document is a Standards Track, Work Group work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
It was created using the Master Template Guide version 1.0. Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>

 

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This is the FINAL version of the Power Vector Intrinsic Programming Reference specification version 1.0.0_final.

The purpose of this document is to provide a guide for vector programming on OpenPOWER systems, with an emphasis on examples of best practices. It further provides a reference for intrinsics provided by compliant compilers on OpenPOWER systems.

This document is a Standard Track, Work Group Specification work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0. Comments, questions, etc. can be submitted to the public mailing list for this document at [email protected].

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This is the review draft of the Linux on Power Architecture Reference version 2.9_pre7

The purpose of this document is to detail a stable platform architecture to be used by platforms defined by the POWER ISA Specification.

This document is a Standard Track, Work Group Specification work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0. Comments, questions, etc. can be submitted to the public mailing list for this document at [email protected].

Please note the full indexed HTML version of the LoPAR document will be uploaded shortly – we are resolving a minor website issue.  For now please refer to the PDF

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This document represents the public review draft for the next version of the OpenPOWER IO Design Architecture (IODA) Version 2 WG Specification.  It consists of markups identified and agreed upon by the Hardware Architecture Work Group.  Comments should be posted to the document mailing list at [email protected].

The purpose of the I/O Design Architecture, version 3 (IODA3) specification is to describe the chip architecture for key aspects of PCI Express® (PCIe)-based host bridge (PHB) designs for IBM® POWER9™ systems.

**The Public Review for this document completes at close-of-business on June 19, 2020.**

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This document represents the public review draft for the next version of the Coherent Accelerator Interface Architecture (CAIA) version 1.0 specification.  It consists of markups identified and agreed upon by the Hardware Architecture Work Group.  Comments should be posted to the document mailing list at [email protected].

This document defines the Coherent Accelerator Interface Architecture (CAIA) for the IBM® POWER9 systems. The information contained in this document enables various CAIA-compliant accelerator implementations to meet the needs of a wide variety of systems and applications. Compatibility with the CAIA enables applications and system software to migrate from one implementation to another with minor changes.

**The Public Review for this document completes at close-of-business on June 19, 2020.**

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The purpose of the POWER ISA – OpenPOWER Profile Compliance Test Harness and Test Suite (TH/TS) Specification, Revision 2.0 is to provide the test suite requirements to be able to demonstrate OpenPOWER ISA Profile, Revision 2.0 compliance for POWER9 systems. The input to this specification is the IBM POWER ISA Version 3.0 B. Implementation of all of the ISA is required. There are no optional sections.

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The Marvell® FastLinQ® 41000 Series 10/25GbE Ethernet NICs (previously known as QLogic FastLinQ) provide exceptional value in delivering industry-leading features and performance to enable the most efficient and agile software-defined data centers (SDDNs). Designed for the most demanding server and network virtualized environments, the 41000 series adapters enable Universal RDMA (RoCE and iWARP) as well as NPAR, VXLAN/NVGRE/GENEVE, and SR-IOV to boost server CPU efficiency and maximize application performance. Range of connectivity options include 10/25GbE SFP/SFP28 optical or direct attach copper (DAC) and 10GBASE-T RJ45.

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Engineered for AI inference, the IBM Power System IC922 provides the compute-intensive and low-latency infrastructure you need to unlock business insights from trained AI models. The POWER9-based Power IC922 provides advanced interconnects (PCIe Gen4, OpenCAPI) to support faster data throughput and decreased latency. Accelerated, the Power IC922 supports up to six NVIDIA® T4 Tensor Core GPU accelerators.

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PowerEL stands for Power Enterprise Linux, it originates from a requirement to have a fully free open source distribution for the IBM POWER 8 and higher platform.
The distribution takes it’s inspiration and origin from various Open Source Enterprise Linux distributions such as Red Hat, CentOS, Oracle Linux, Fedora, SuSE, and others.
PowerEL has been optimized for specific CPU features, such as IBM Power8 or higher and Intel x86 AVX or higher, so it only works on cpu’s with at least this set of features available.
PowerEL provides a very convenient way of more packages out of the box.
PowerEL uses the distro tag pel and uses the same ABI as the open source rhel based systems, so you can use existing binaries on PowerEL.

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Superior system computing power
· Support 8 V100 or 20 T4 GPUs to provide full-field superior heterogeneous computing power
· Support 2 POWER9 Sforza processors with up to 44 cores and 176 threads, providing superior scheduling capability
· Tuning for specific deep learning models, performance up to 20% compared to equivalent X86 platforms
· Fully compatible with FPGA/AISC, providing application-specific acceleration
Ultra-high computing density for significant TCO savings
· Compared to regular 2U 4GPU servers, double computing density
· Supporting the same number of GPUs and comparing to lower-density GPU server cluster , FP5468G2 space saved by 50%, power saved by 23%, measured computing power increased by 8%, price reduced by 34%, for 500 server clusters can save TCO over 10 million dollars
Flexible heterogeneous topology
· Support three topologies – balance, common and cascade
· Flexible topology switching based on application scenarios/training models
Efficient , high-volume local storage and high-speed IO expansion
· Support up to 24 3.5”hard drives, 6 of which support U.2 NVMe SSD providing high read and write speed
· Support 4 standard PCIe x16 slots, providing 100Gb RDMA high speed network

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Parallelware Analyzer is a suite of command-line tools aimed at helping software developers to build better quality parallel software in less time. Designed around the needs of developers, Parallelware Analyzer provides the appropriate tools for the key stages of the parallel development workflow, aiding developers with code analysis that would otherwise be error-prone and completed manually. It can also be easily integrated with DevOp tools to benefit from its automatic usage during Continuous Integration.

The unmatched state-of-the-art static code analysis capabilities of the Parallelware technology address the complexity of parallelism from three different perspectives: finding parallel defects in the code, discovering new opportunities for parallelization in the code, and generating parallel-equivalent code that enables tasks to complete in less time. The Parallelware analysis completes quickly and enables real-time static code analysis for the development of correct parallel software.

 

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Helios is a powerful B2B technology to allow searching of large commercial music libraries by using music itself as the search key. There are many uses for Helios. Here are a few examples.

* You have a digital jukebox in bars, restaurants, and pubs. You want venue patrons to be able to play more music like whatever they just paid to hear.

* You have a music catalogue management platform that publishers and labels use to track their digital assets. Your customers want to be able to search within their own catalogue using your slick platform.

* You have an online digital music store and you’d like to be able to make intelligent product recommendations to your customers based on what songs they’ve already got in their shopping cart before they check out.

* You have a streaming music service whose DJs need inspiration for coming up with either channel based or custom curated playlists faster.

* You market software for DJs, such as plugins to manage their library. While they’re playing live a plugin in their favourite software suggests some tracks to mix or play next.

* You have a commercial music library of any size. Perhaps you are a major record label, perhaps independent, or maybe you’ve amalgamated music from multiple labels, independent artists, or publishers. You need to assist your clients obtain synchronization licenses quickly for appropriate pieces of music for their film, TV, documentary, commercials, video games, or some other context.

There are countless other examples, but let’s talk about this last one. Nearly always your client approaches you with samples already in hand. “Hey, do you have anything like this?” This could be an MP3 or a YouTube video URL. Because Helios allows you to search the catalogue using music itself as the search key, you could use the customer’s samples directly to help them find what they’re looking for.

Traditionally, in the absence of such technology, the way this has been done for decades may surprise many. It is both costly and involves many hours or even days of manual human labour which delays the business process. The business must manually search, usually using textual tags, and listen to a great deal of irrelevant music in the hopes of finding the one the client is actually willing to spend money on.

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HAIECON created a platform combining elements of Artificial Intelligence with Extended Intelligence and Cognitive procedures which as a result creates commodity class asset applicable in financial sector. This particular solution uses cognitive frameworks for individual loan applicant modelling, clients ratings and best recovery strategy recommendation. For clients rating, HAIECON is using more than 300 parameters and final success rate is 13% better than other solutions in Brazil!

IBM Cloud Private and AC922 are key components of hybrid cloud architecture. IBM Watson is used for sentiment analysis. Clients data need to be kept in private cloud – as per Brazilian data regulation – for each company who want to use this solution for credit assessment and managing non-performing loans.

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Ultra high performance and density
* Supports 2 POWER9 Sforza processors in 1U space, providing up to 44 cores and 176 threads
* Supports 16 DDR4 2666MHz memories per unit , up to 2TB memory capacity
* Supports NVMe SSD, providing 10 times IOPS of SATA SSD

Strong expansion capability
* 4 3.5″ HDD per unit, providing up to 48TB of storage capacity
* Up to 2 PCIe4.0 slots, supporting CAPI 2.0 acceleration interface
* Supports OCP device, realizing flexible network architecture

Intelligent management
* Supports intelligent air-cooled technology and perform accurate and real-time monitoring and control of system power consumption
* Supports web management interface and rapid diagnosis method, monitoring system parameters through BMC, ensuring system stable and reliable

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The purpose of the OpenPOWER Architecture Compliance Definition document is to give a consistent approach to compliance under the guidance of the Compliance Work Group. It contains the following:
• Document the OpenPOWER specifications that contain the interfaces that are required to be OpenPOWER compliant
• Document an overview of the Compliance Test Harness and Test Suite Specifications that have been developed in the Compliance Work Group, and an outline of the contents expected in each specification
• Document procedures on how to measure and document compliance and where to submit the report for compliance

 

Version 1.1.0 of the document is based on the POWER8™ systems and the POWER9™ systems and reflects work by the Compliance Work Group to improve the document.

 

The OpenPOWER Architecture Compliance Definition document is a Standards Track, Work Group Specification owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. Comments about this document may be submitted to the Compliance Workgroup by emailing to <[email protected]>

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The TELEMAC-MASCARET system is a powerful integrated modelling tool for use in the field of free-surface flows. Having been used in the context of very many studies throughout the world (several hundred to date), it has become one of the major standards in its field.
The various simulation modules use high-capacity algorithms based on the finite-element method. Space is discretised in the form of an unstructured grid of triangular elements, which means that it can be refined particularly in areas of special interest.
Parallelization on distributed memory machines is handled by MPI.

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Ultra-high density

• 4U storage server supporting 40x 3.5″ HDDs and 480T storage capacity
• M.2 SSDs, install OS system here to enhance booting speed astonishingly.
• SSDs , caching or meeting additional storage needs

 

Excellent computing performance

• Supports 2 POWER9 Sforza processors, up to 44 cores and 176 threads per unit
• Supports 16 DDR4 2666MHz memories per unit , up to 1TB memory capacity
• Up to 8 PCIe4.0 slots, supporting CAPI 2.0 acceleration interface

 

Scale with software-defined storage

• Distributed storage system support Ceph,inspur AS13000, IBM GPFS , offering economic solutions and management of capacity expansion
• Built for the evolution and growth of unstructured data, file and object storage solutions address requirements with data protection, future-proof flexibility

 

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This is a 2-socket POWER9 server with 4 to 6 GPUs attached via a high speed, high bandwidth low latency CPU link.

 

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P225P – 2 x 25/10GbE PCIe NIC – High-Performance, Feature-Rich NetXtreme® E-Series Dual-Port 25GbE PCIe Ethernet NIC

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Qlogic QLE2742 Dual-Port Gen 6 (32GFC) Fibre Channel Adapter, low profile, PCIe® 3.0 x8

• Industry’s first Gen 6 FC HBA available in single, dual, and quad-port versions
• Two ports of Gen 6 FC deliver 12,800MBps aggregate throughput
• Up to 1.3 million IOPS fuel high performance in AFA and high-density virtualized environments
• FC-NVMe capability allows simultaneous access to NVMe™ and FCP Storage on the same port
• Enhanced reliability, diagnostics, and accelerated deployment powered by QLogic StorFusion™ technology
• Port isolation design offers deterministic and scalable performance on each port

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Qlogic QLE2692 Dual-Port Enhanced Gen 5 (16GFC) Fibre Channel Adapter, low profile, PCIe® 3.0 x8:

• The latest and most advanced 16GFC HBA from QLogic®, available in single- and dual-port versions
• Up to 1.3 million IOPS fuel high performance in AFA and high-density virtualized environments
• FC-NVMe capability allows simultaneous access to NVMe™ and FCP Storage on the same port
• Enhanced reliability, diagnostics, and accelerated deployment powered by QLogic StorFusion™ technology
• Port isolation design offers deterministic and scalable performance on each port

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Superior Performance

• OpenPOWER9 LaGrange CPU, 2 Sockets up to 44 cores(2.9Ghz) and 176 threads
• Ultra high CPU interconnect bandwidth
• Next Gen PCIe – PCIe Gen4 2x faster vs PCIe Gen3

 

Optimized for Heterogeneous computing

• NVLink2.0 – higher bandwidth and lower latency for GPU to CPU
• OpenCAPI – higher bandwidth and lower latency for FPGA/ASIC to CPU

 

Optimized for memory computing

• Up to 16 memory channels offering higher bandwidth
• Up to 32 DDR4-2666 DIMM Slots offering max 4TB capacity

 

High cost performance

• Low TCO through system optimization of cooling and power supply, industry standardization and more flexible service and support

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Modular design optimized for scale-out deployments , hybrid cloud, big data and enterprise AI acceleration built on open standards-based system.  Key features:

• Gain the performance and capabilities of IBM® POWER9™ “Sforza” CPU combined with the cost advantages of industry standardization, 2 sockets for up to 44 cores (2.75Ghz).
• Higher memory capacity and bandwidth, up to 1TB of memory with 16 DDR4-2666 DIMM slots.
• Next Gen PCIe – PCIe Gen4 2x faster vs PCIe Gen3.
• Modular design optimized to scale from single racks to hundreds of racks for large-scale clusters and scale-out deployments.
• Acceleration of big data workloads with support for 12 large form factor drives or 24 small form factor drives.
• Designed to fully exploit the capabilities of GPU accelerators, up to 4 NVIDIA® V100 PCIe-based GPU in 2U chassis.
• 8x PCIe Gen4 slots，maximize application performance and eliminate I/O bottlenecks.
• Support OCP NIC, providing 25G, 10G, 1G and more flexible network options.
• Realize low cost of acquisition and the ability to achieve superior economics.
• Low acquisition cost through system optimization OpenPOWER innovation, industry standardization, more flexible service and support.

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The FP5295G2 has a new architecture , pairing POWER9 CPUs and NVIDIA Tesla V100 NVLink GPUs and delivering up to 5.6x times the performance for each pairing. NVLink can share Memory for CPU –GPU which provides simplified deep-learning deployment and performance.

Supports PCIe Gen4、CAPI 2.0 and OpenCAPI.

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The cognitive era is driving Linux® workloads that require superior data throughput and storage capacity needed to meet the challenges of the AI era. IBM® Power Systems™ LC922 is purpose built to meet those requirements with a storage-rich server design that delivers industry-leading compute to analyze and explore data with the vast storage capacity to contain it. LC922 enables faster access to data and scaling efficiency with POWER9™ advanced IO architecture, including PCI Express (PCIe) 4.0 to help companies gain new business insights and competitive advantages. With the ability to meet diverse needs, the server is built on open standards and incorporates accelerators.

 

This 2-socket, 2U POWER9 system was developed from OpenPOWER system reference designs, uses OpenPOWER firmware from git-hub and complies with OpenPOWER specifications.

 

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The cognitive era is driving Linux workloads that require superior data throughput and density to meet the challenges of the AI era. IBM Power Systems LC921 is purpose built to meet those requirements with POWER9™ advanced IO architecture, including PCI Express (PCIe) 4.0 to help companies gain new business insights and competitive advantages. With the ability to meet diverse needs, the server is built on open standards and incorporates accelerators.

 

This 2-socket, 1U POWER9 system was developed from OpenPOWER system reference designs, uses OpenPOWER firmware from git-hub and complies with OpenPOWER specifications.

 

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IBM Power Systems S821LC brings open innovation and high-density computing to the Linux server market. It offers superior virtualization and incorporates POWER8 processors, accelerators, and faster I/O using Coherent Accelerator Processor Interface (CAPI) technology. The server optimizes processing power, offers increased workload throughput and reduces datacenter floor space requirements. With the ability to meet diverse needs, the server is built on open standards and incorporates accelerators.

 

This 2-socket, 1U POWER8 system was developed from OpenPOWER system reference designs, uses OpenPOWER firmware from git-hub and complies with OpenPOWER specifications.

 

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The IBM Power S822LC for Big Data provides industry-leading performance, data throughput and virtualization with a flexible design to meet broad workload requirements. With the ability to meet diverse needs, the server is built on open standards and incorporates accelerators.

This 2-socket, 2U POWER8 system was developed from OpenPOWER system reference designs, uses OpenPOWER firmware from git-hub and complies with OpenPOWER specifications.

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The OpenCAPI Power Platform Architecture (OPPA) defines an accelerator interface structure for coherently attaching accelerators to the IBM Power Systems™ using an OpenCAPI Physical Link. The intent is to allow implementation of a wide range of accelerators to optimally address many different market segments. The target audience is firmware and operating system developers.

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SUSE Linux Enterprise Server (SLES) for Power is an open-source Linux operating system built on top of the free and open source Linux kernel and is distributed with system and application software from other open source projects. SLES for Power is available for computer systems based on IBM Power processors and is available in big-endian (SLES 11) and little-endian (SLES 12 and SLES 15) variants.

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The OpenPOWER Foundation documentation template provides a framework for OpenPOWER public and private documentation. The goal of this document is to promote community contributions to OpenPOWER documentation and to enable new contributions within a common look and feel.

 

The major sections of this document addresses the following topics:

• Getting started
• Creating a new document
• Modifying an existing document
• Debugging build failures
• Publishing OpenPOWER Documents
• Understanding the project structure
• Policies and conventions
• Frequently asked questions
• Common git commands
• Finding more information

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The purpose of the OpenPOWER Advanced Accelerator Adapter Compliance: 25G I/O Test Harness and Test Suite specification is to provide the test suite requirements to demonstrate OpenPOWER Advanced Accelerator Adapter 25G I/O compliance for POWER9™ systems.

 

The input to this specification is the following specification:

• OpenPOWER Advanced Accelerator Adapter Electro-Mechanical Specification which describes electro-mechanical specification for advanced accelerator adapters within the OpenPOWER ecosystem supported by IBM POWER9..

 

There are two accelerator approaches for the 25Gbit/sec interface and the compliance for each approach is defined in this document. The first approach is a Mezzanine Adapter Card which is attached to the system planar via two connectors. The Mezzanine Adapter Card for OpenPOWER systems based on the POWER9 processor attaches to the 25Gbit/sec interface native to the POWER9 and plugs into the mezzanine card connectors.

 

The second approach is a Cabled Interface Extension to an adapter card. It uses a PCIe card as an example but the cabled extension does not require the adapter card be PCIe. POWER9 platforms support the optional cabling of the 25Gbit/sec Advanced Accelerator Interface to the advanced accelerator adapter in a riser card plugged into a PCIe slot in the same system. In addition, the adapter could be located in different drawer of the rack.

 

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.

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基于容器技术打造云原生应用产品体系，立足企业开发、测试及IT管理需求，提供一站式容器云平台，为企业提供轻量、快速、高效、友好的服务运行及开发环境，助力企业IT架构升级。

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Kyligence provides a leading intelligent OLAP platform powered by Apache Kylin to enable interactive big data analytics with high concurrency from on-premises to the cloud.

 

Kyligence flagship product Kyligence Enterprise, powered by Apache Kylin, brings instant insights on massive datasets for business users and data analysts. With cutting-edge machine learning technology and intelligent data modeling functionality, it greatly improves productivity of big data analytics.

 

Kylgience’s core strengths include:
1. Blazing Performance
2. Intelligent Auto-modeling
3. Unified Data Analytics Platform

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The ADM-PCIE-9V3 features a 16 lane PCIe Gen3 or 8 lane Gen4 capable interface, which allows for maximum data throughput. The ADM-PCIE-9V3 is equipped with front IO via 2x QSFP28 sockets, each supporting one 100GbE or four 25GbE interfaces. Full profile card slots can also support two additional 100GbE interfaces via Samtec FireFly® modules, allowing this board to become a massive network device with 4x 100GbE ports. The board also includes two 1G x72 DDR4-2400 ECC memory banks each provide 8GiB of on-board DDR4-2400 memory (72 bits wide). System monitoring of temperature, voltage, and current gives developers accurate feedback of power utilization for their designs. An optional Board Support Package (BSP) with example FPGA designs, application software, mature Application Programming Interface (API) and driver support for MS Windows and Linux is available. The ADC-PCIE-9V3 comes with low-profile and full-height front brackets (low-profile bracket fitted as standard) and an optional blower for low air-flow systems.

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Talos II mainboard. Dual POWER9 Sforza with 16 DDR4 DIMM slots and 5 PCIe Gen 4 slots.

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The ADM-PCIE-9V3 features a 16 lane PCIe Gen3 or 8 lane Gen4 capable interface, which allows for maximum data throughput. The ADM-PCIE-9V3 is equipped with front IO via 2x QSFP28 sockets, each supporting one 100GbE or four 25GbE interfaces. Full profile card slots can also support two additional 100GbE interfaces via Samtec FireFly® modules, allowing this board to become a massive network device with 4x 100GbE ports. The board also includes two 1G x72 DDR4-2400 ECC memory banks each provide 8GiB of on-board DDR4-2400 memory (72 bits wide). System monitoring of temperature, voltage, and current gives developers accurate feedback of power utilization for their designs. An optional Board Support Package (BSP) with example FPGA designs, application software, mature Application Programming Interface (API) and driver support for MS Windows and Linux is available. The ADC-PCIE-9V3 comes with low-profile and full-height front brackets (low-profile bracket fitted as standard) and an optional blower for low air-flow systems.

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Data center, cloud and high-performance computing environments not only require large amounts of storage capacity, they also must provide the data protection, flexibility and performance today’s applications and end users demand. The MegaRAID 9460-16i Tri-Mode Storage Adapter is a 12Gb/s SAS/SATA/PCIe (NVMe) controller card that addresses these needs by delivering proven performance and RAID data protection for a range of high-end server storage applications.

 

Broadcom’s Tri-Mode SerDes Technology enables the operation of NVMe, SAS or SATA devices in a single drive bay, allowing for endless design flexibility.

• Connect up to 240 SAS/SATA devices or 24 NVMe devices per controller
• Fits into rack-mounted servers with low-profile form factor and side-mounted SAS connectors
• Support critical, high-bandwidth applications with PCIe® 3.1 connectivity
• Balance protection and performance for critical applications with RAID levels 0, 1, 5, 6, 10, 50, and 60
• Add more protection and peace of mind with CacheVault® flash cache protection

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The document provides a detailed focus on the base design requirements of an FPGA-based accelerator card utilizing CAPI 2.0. The document is a dynamic document that will be enhanced over time. OpenPower members are invited to add information, ideas and approaches to the document. The Appendix has an open structure and implementations like adding a new FPGA or adding a common function block.

Please provide your input to  first for discussion. Comments, questions, and suggestions for improvement can be submitted to the the OpenPower Accelerator Workgroup public mailing list for this document at [email protected].

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P93D2-2P (MiHawk) is a 2U2S Power9 server made by Wistron Corporation. With 2 LaGrange processors inside, MiHawk has up to 10 PCIe slots (including 4 of PCIe Gen4 and 6 of PCIe Gen3) and 4 OpenCAPI connectors for I/O throughput. On storage, we provide both LFF/SFF two type drive bays and multiple combination of SAS/SATA/U.2 NVMe for customers to choose. By the high-speed I/O and flexibility features, MiHawk has confidence to fulfill any kind of purpose such as AI, Big Data, and HPC.  More information can be found in MiHawk product brief.

 

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Neokylin Advanced System(Virtualization Edition) is specialized for enterprise data center, possessing functions like virtualization management, dynamic migration, high availability protection, load balance and energy-saving dispatching. It can increase data utilization, decrease energy consumption and breakdown rate, and improve manageability of application system. Therefore, Virtualization edition is the best strategic choice for users requesting lower cost, faster reward and free application model.

 

The Desktop Virtualization for Neokylin secure cloud operating system dedicates to solve problems in running desktop system, such as the difficulties in controling enterprise information scattered in desktop system, high cost but low efficiency of IT maintenance and high energy consumption. With virtualization, all the data was collected and stored into the clustered data center, to ensure the confidentiality, simplify the deployment and maintenance of hardware and software, and save a lot of electricity.

 

NeoKylin Linux Security OS is self-determination, controlled and high grade security Operating System software, which is based on LSM mechanism of SELinux subsystem framework, provides the privilege management function by Separation of the Three Powers, customized system security based on customers requirement. It provides the unified Security Management Centre(SMC), which supports security mode switching, the important data encryption storage, management of privilege users, personal Identification based two-factor certification, the least privilege of process, Type-Based Access Control with role, network safety protection, fine grain Security Auditing, delete the files in security, etc. It takes all-directional system safety protection for subscriber of government and enterprise.

 

NeoKylin Linux Advanced Server Operating System comes with several kernel-level features and power management capabilities that let you get the maximum performance from your systems. These features lead to greater performance for your critical workloads and processes. NeoKylin Linux Advanced Server provides management tools which easily to deploy database and middleware. It’s easy for the manager to monitor memory, storage and networking resources through Integrated monitor tool based on web in real time. NeoKylin Linux Advanced Server is a versatile platform that can be deployed on physical systems, as a guest on the major hypervisors, or in the cloud. It also includes a complete LAMP stack (Apache/Tomcat, PHP/Perl/Python, MySQL/PostgreSQL), file and print services (NFS, CIFS/SMB, CUPS), and authentication services (openldap, kerberos5).

 

Based on the HA software products of NeoKylin Server Software, NeoKylin HA Cluster Software, with three advantages of “reliable system”, “reliable data” and “reliable applic hardware and software systems and the stability and reliabilitation”, aims to achieve HA protection for business systems, improvesy of applications running, provides the anti-fault system to support the reliability requirements of the key business systems and provides users with efficient and reliable services.

 

Neokylin Linux Advanced Server Operating System V7 Update2 (NKAS V7U2) was developed by CS2C with years of Linux developing experience, NKAS V7U2 is a Chinese Linux Operating System with various functions, high security, easy management and high performances, catering to business performance, expansibility and performance requirements at the virtualization, cloud computing and big data times,. It is based on CMMI5 standard, aimed at key business and data workload and widely deployed in physical and virtualized environment, public cloud platform, private cloud as well as hybrid cloud environment.

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Solution for Face Recognition and Mood Recognition running on AC922 Server with NVIDIA V100 GPUs, Operating System Red Hat Enterprise Linux 7.4, compiled using the IBM Advance Toolchain.

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An applications that combines facial recognition, objects detection and computer vision with a neural network to extract useful insights.

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The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It uses 14 nm technology with 17 metal layers. The POWER9 processor supports direct-attach memory. It supports a maximum symmetric multiprocessing (SMP) size of two sockets and is targeted for scale-out workloads. This user’s manual describes the POWER9 processor and provides information about the registers, facilities, initialization, and use of the POWER9 processor. This document focuses primarily on the microprocessor core and the storage subsystem.

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This user’s manual describes the IBM POWER8 processor single-chip module (SCM) features, facilities, components, and use. It provides information about the POWER8 processor from a programming model point of view, and is intended to be a companion to the Power Instruction Set Architecture (ISA) documentation. This document focuses primarily on the microprocessor core and the storage subsystem. It is intended for system software and hardware developers and application programmers.

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This document provides errata against version 1.4 of the OpenPOWER ELF v2 Application Binary Interface Specification. These errata should be considered part of said specification until such time as a newer version of the full specification is published.

This document is a Non-standard Track, Work Group Note work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. Comments, questions, etc. can be submitted to the public mailing list for the parent specification at <[email protected]>.

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The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

This Host-Bus adapter is used to connect the ExpEther40G I/O Expansion Unit (N8141-80F, N8141-81F) to a host server vi an Ethernet. Please see the material of the I/O Expansion Unit.

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The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

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The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

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The goal of this project is to provide functional equivalents of the Intel MMX, SSE, and AVX intrinsic functions, that are commonly used in Linux applications, and make them (or equivalents) available for the PowerPC64LE platform.

 

This document is a Work Group Note work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.

 

Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.

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The purpose of the OpenPOWER FSI Compliance Test Harness and Test Suite (TH/TS) Specification is to provide the test suite requirements to be able to demonstrate OpenPOWER FSI compliance for POWER8™ and POWER9™ systems. The input to this specification is the following specification:

• Field Replaceable Unit (FRU) Service Interface (FSI) – OpenFSI Specification which describes the FSI Protocol in detail, including the timing and electrical specification.

 

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.  Comments, questions, etc. can be submitted to the public mailing list for this document at <openpower-fsi–[email protected]>.

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The purpose of the OpenPOWER CAPI 2.0 Accelerator Compliance: Test Specification is to provide the test suite requirements to demonstrate OpenPOWER CAPI 2.0 Accelerator solution compliance for POWER9™ systems. The input to this specification are the following specifications which define the hardware interfaces which are the subject of this OpenPOWER CAPI 2.0 Accelerator Compliance document:

1. OpenPOWER Power Service Layer (PSL) to Accelerator Function Unit (AFU) Interface CAPI 2.0 Specification, Revision 1.0 which describes the interface to communicate to the acceleration logic running on the FPGA.
2. OpenPOWER Coherent Accelerator Interface Architecture Version 2 (CAIA 2) Specification which describes a coherent accelerator interface structure for coherently attaching accelerators to the POWER9 systems using a standard PCIe bus.

 

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.   Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.

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The OpenPOWER Foundation set up the OpenPOWER Ready™ program in 2016.   Within the program, developers identify products for use by members of the OpenPOWER ecosystem.    The OpenPOWER Ready mark indicates that a product should work with other OpenPOWER Ready products.  Because of this the OpenPOWER Foundation is suggesting that entities providing such products join the foundation.

 

The OpenPOWER Ready Definition and Criteria – V2.0 document describes the details of the program.    Since there are several types of products categorized in the document they are listed below.  Because of the differences between the categories of products the criteria varies between them.  Developers will find the categories and criteria described in the document.

 

OpenPOWER Ready Product Categories

• Systems
• CAPI Accelerators – Heterogeneous accelerator attached via a CAPI enabled PCIe Adapter
• Software (Operating Systems, tool chain, and applications)
• IO Adapters – storage controllers and network controllers are examples of IO Adapters
• CAPI Adapters
• OpenCAPI™ 3.0 Adapters
• System Support Components

 

Companies and other entities can make a strong statement about their support of the OpenPOWER technology as an alternative to other server solutions by becoming a member of the OpenPOWER Foundation membership.

 

This document is a Standard Track, Work Group Specification work product owned by the OpenPOWER Ready Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.  Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.

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The Advanced Accelerator Adapter Electro-Mechanical Specification defines an electro-mechanical specification for advanced accelerator adapters within the OpenPOWER eco-system supported by IBM® POWER9™.  POWER9 modules present a 25Gbps interface organized into groups of 8 bit-lanes. Innovation within the community is encouraged for systems that support accelerated computing and the accelerator adapters needed to make heterogeneous / accelerated computing solutions available to the market.

 

This specification defines two accelerator approaches. The first approach is a mezzanine card attached to the system planar via two connectors. This approach is defined in Part I: Mezzanine Adapter Card.

 

The second approach is via cable and is defined in Cabled Interface Extension. While the accelerator card form factor is not defined in this specification Part II: Cabled Interface Extension assumes a PCIe® card for illustration.

 

The electrical characteristics of the 25Gbps channel are defined in Part III: 25 Gbit/sec Electrical Channel.

 

This document is a Standard Track, Workgroup Specification work product owned by the 25G IO Interoperability Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Document Development Guide version 1.1.0.  Comments, questions, etc. can be submitted to the public mailing list for this document at

<[email protected]>.

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Software solution for High Availability preventing data loss and protecting your IT system which finally leads to saving time and money.

 

EXPRESSCLUSTER X is supported on POWER9 and prior.

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The purpose of this document is is to define a method and a template to collect Physical Science use cases from scientists and research engineers working on Physical Science projects in the context and within the scope of the OpenPOWER Foundation for Physical Science Workgroup.

An effective method that is shared by all stakeholders and participants could contribute to:

• Understanding the workflow, starting with user expectations
• Helping Physical Science projects maintain costs within a chosen envelope
• Mapping the functionalities to the scientific requirements
• Removing possible misunderstanding between the scientific community and ICT stakeholders.

This document is a Non-standard Track, Work Group Note work product owned by the OpenPower Workgroup for Physical Science.
Comments, questions, etc. can be submitted to the public mailing list for this document at
<[email protected]>

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The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

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The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

This Host-Bus adapter is used to connect the ExpEther40G I/O Expansion Unit (N8141-80F, N8141-81F) to a host server vi an Ethernet. Please see the material of the I/O Expansion Unit.

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The technology innovation of ExpEther expands the power of the PCI Express switch beyond the computer chassis via Ethernet without modification of existing hardware and software. ExpEther 40G devices delivers a compelling solution for real-time Big Data processing and other data center workload acceleration. It does so by enabling the connection of GPGPU, NVMe SSD, or FPGA-based accelerators via an Ethernet connection. Please visit the ExpEther consortium. http://www.expether.org/

These I/O Expansion Unit are connected to the host server via a standard Ethernet by the ExpEther40G Host-Bus adapter (N8104-165). Please see the material of this Host-Bus adapter.

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The world’s first OpenPOWER enterprise class high-performance 4-socket server designed for data intensive applications with outstanding footprint.

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Parallelware Trainer is an interactive training tool designed to facilitate the learning, usage, and implementation of parallel programming. It provides an integrated development environment (IDE) that gives users targeted advice on sections of code that can be successfully parallelized, along with the ability to test the performance improvements of particular parallel implementations.

By quickly and efficiently identifying areas for possible parallelism this tool is not only useful for those learning about parallel programming, but also to aid more experienced developers as the Trainer increases the speed of understanding the software and testing possible parallelism methods. The power of modern heterogeneous hardware including multi-core CPUs and GPUs can be exploited through different paradigms ‒ such as multi-threading or tasking ‒ and using standards such as OpenMP or OpenACC.

Furthermore, Parallelware Trainer looks for defects in your code as well as potential issues related to parallelism, reporting recommendations on how to fix them right from the integrated code editor.

 

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This paper describes how to port various pre-built application binaries used in BWAKIT into OpenPOWER architecture and execute the BWAKIT pipeline successfully.

 

Next Generation Sequencing (NGS) technology produces large volume of genome data, which gets processed using various open source Bioinformatics tools. The configuration and compilation of some of the bioinformatics tools (e.g. BWAKIT, root) are challenging, requiring application porting for some architectures (e.g. IBM Power). Moreover, the application porting should not change the semantics of the program and output generated from different architectures should be similar across different architectures. Burrows-Wheeler Aligner (BWA) is the most popular genome mapping application used in BWAKIT toolset. The BWAKIT provides pre-compiled binaries for x86_64 architecture and end-to-end solution for genome mapping.  This paper describes how to port various pre-built application binaries used in BWAKIT into OpenPOWER architecture and execute the BWAKIT pipeline successfully.  In addition, it reports the validation of the output results on OpenPOWER to confirm the successful porting of BWAKIT.

 

Note:  This paper is the result of collaboration within members of the Personalized Medicine Workgroup and Sidra medical and Research Center.

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The POWER Service Layer to Accelerator Functional Unit (PSL / AFU) interface communicates to the acceleration logic running on the FPGA. Through this interface, the PSL offers services to the AFU. The services offered are cache-line oriented and allow the AFU to make buffering versus throughput trade-offs.

The interface to the AFU is composed of six independent interfaces:
• AFU Command Interface is the interface through which the AFU sends service requests to the PSL.
• AFU Buffer Interface is the interface through which the PSL moves data to and from the AFU.
• PSL Response Interface is the interface through which the PSL reports status about service requests.
• AFU MMIO Interface is the interface through which software reads and writes can access registers within the AFU.
• AFU Control Interface allows the PSL job management functions to control the state of the AFU.
• AFU DMA Interface allows the AFU to send native PCIe Writes and Reads and to receive Read Completion data.

Together these interfaces allow software to control the AFU state and allow the AFU to access data in the system.

This document is a Standard Track, Work Group Specification work product owned by the Accelerator Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0. Comments, questions, etc. can be submitted to the public mailing list for this document at
<[email protected]>.

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The OpenPOWER Memory Bus Specification defines the OpenPOWER Memory Bus Architecture.  The architecture and spec are used to develop Memory Function Units(MFU) and to integration of those MFUs into the OpenPOWER system structure. An MFU is a logic block developed by a member of the OpenPOWER eco-system to attach special purpose memory technology and function processing for data stored in the memory technology.  An example of MFU might be a database function accelerator which attaches dense flash memory technology.  This figure illustrates the concept.

 

Comments regarding the specification content and suggestions for updates may be submitted to the following mailing list:

<[email protected]>

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The MegaRAID® SAS 9380-8i8e, with eight internal and eight external ports
in a low-profile form factor, delivers two 1.2 GHz PowerPC processor cores
and a 72-bit DDR3 interface that drives 2 GB cache memory. Powered by
the SAS3316 dual-core ROC, with 16 native SAS/SATA ports, the 9380- 8i8e
controller can take full advantage of the latest PCI Express 3.0 interface
to provide higher performance and increased throughput. The 12 Gb/s
MegaRAID SAS 9380-8i8e is designed to direct connect eight drives
inside the box or eight drives outside the box. By leveraging SAS expander
technology, users can expand to up to 240 drives increasing inside the box
drive count or through supporting external JBOD storage enclosures.

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The MegaRAID® SAS 9361-24i, with twenty-four internal ports in a lowprofile*
form factor, delivers two 1.2 GHz PowerPC processor cores and a
72-bit DDR3 interface that drives 4 GB cache memory. Powered by the
SAS3324 dual-core ROC, with 24 native SAS/SATA ports, the 9361-24i
controller can take full advantage of the latest PCI Express 3.0 interface
to provide higher performance and increased throughput. The 12 Gb/s
MegaRAID SAS 9361-24i is designed for configuring high-density storage
servers with up to 24 drives via direct connection inside the box or up to
240 drives by leveraging SAS expander technology.

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The Avago MegaRAID® SAS 9361-16i, with sixteen internal ports in a lowprofile
form factor, delivers two 1.2GHz PowerPC processor cores and a
72-bit DDR3 interface that drives 2GB cache memory. Powered by the
SAS3316 dual-core ROC, with 16 native SAS/SATA ports, the 9361-16i
controller can take full advantage of the latest PCI Express 3.0 interface
to provide higher performance and increased throughput. The 12Gb/s
MegaRAID SAS 9361-16i is designed for confi guring high-density storage
servers with up to 16 drives via direct connection inside the box or up to
240 drives by leveraging SAS expander technology.

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This document provides requirements on a test implementation targeting the Application Binary Interface (ABI) for OpenPOWER. Currently, this test implementation is shipped with the gcc sources, and so forms part of the official gcc build and test process.

 

The OpenPOWER ELFv2 Application Binary Interface (ABI) Compliance Test Harness and Test Suite (TH/TS) Specification provides the test suite requirements to demonstrate compliance with the OpenPOWER 64-bit ELFv2 ABI Specification.  It describes the tests required in the test suite and a test harness needed to execute the test suite. It also describes the successful execution of the test suite, including what it means for an optional feature to fail.

 

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0.

 

Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.

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HGST Ultrastar He8 SATA 8TB 3.5-inch Helium Platform Enterprise Hard Disk Drive

SATA 6Gb/s and SAS 12Gb/s

12Gb/s SAS compatible with next gen data centers; backwards compatible with 6Gb/s SAS

2.5M hours MTBF 2 rating & 5-year limited warranty

Instant Secure Erase (ISE) & Self-Encrypting Drive (SED) options

Advanced format 4Kn and 512e models

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HGST Ultrastar® 7K6000 SATA 6TB 3.5-inch Enterprise 7200 RPM Hard Disk Drive

128MB cache buffer improves response time and data management

Instant Secure Erase (ISE) & Self-Encrypting Drive (SED) options

Advanced format 4Kn and 512e models up to 6TB; 512n format available in 4TB and 2TB capacities

2M hours MTBF 2 rating & 5-year limited warranty

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The ABI (application binary interface) specification provides the definitions for the machine interface and inter-object interfaces for the little-endian POWER architecture.

 

This specification defines the OpenPOWER ELF V2 ABI which is derived from and represents the first major update to the Power ABI since the original release of the IBM® RS/6000® ABI. It was developed to make extensive use of new functions available in OpenPOWER-compliant processors. It expects an OpenPOWER-compliant processor to implement at least Power ISA V2.07B with all OpenPOWER Architecture instruction categories as well as OpenPOWER-defined implementation characteristics for some implementation-specific features.

 

The Executable and Linking Format (ELF) defines a linking interface for executables and shared objects in two parts: the first part is the generic System V ABI, the second part is a processor-specific supplement.  This document, the OpenPOWER ABI for Linux Supplement for the Power Architecture 64-bit ELF V2 ABI, is the OpenPOWER-compliant processor-specific supplement for use with ELF V2 on 64-bit IBM Power Architecture® systems. This is not a complete System V ABI supplement because it does not define any library interfaces. This document establishes both big-endian and little-endian application binary interfaces. OpenPOWER-compliant processors in the 64-bit Power Architecture can execute in either big-endian or little-endian mode. Executables and executable-generated data (in general) that subscribes to either byte ordering is not portable to a system running in the other mode.

 

ERRATA:

An OpenPOWER ELFv2 Errata: For ELFv2 ABI Version 1.4 has been published.  These errata should be considered part of this specification until such time as a newer version of the full specification is published.

 

This document is a Standards Track, Work Group work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.

 

Comments, questions, etc. can be submitted to the public mailing list for this document at

<[email protected]>.

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Data center, cloud and high-performance computing environments not only require large amounts of storage capacity, they also must provide the data protection and performance today’s applications and end users demand. The MegaRAID SAS 9361-16i 12Gb/s RAID controller card addresses these needs by delivering proven performance and RAID data protection for a range of server storage applications.

Connect up to 16 SATA or SAS drives via direct connection inside the box or up to 240 drives leveraging SAS expander technology
Fit into rack-mounted servers with low-profile form factor and side-mounted SAS connectors
Support critical, high-bandwidth applications with PCIe® 3.0 connectivity
Balance protection and performance for critical applications with RAID levels 0, 1, 5, 6, 10, 50, and 60
Add more protection and peace of mind with optional CacheVault® flash cache protection.

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2 Terabyte CAPI 1.0 enabled Flash Storage Card
Includes support for CAPI SNAP Near Storage Acceleration
Utilizes 2x onboard M.2 22110 NVMe SSDs

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OpenPOWER Ready™ is a mark used by the OpenPOWER Foundation to enable OpenPOWER ecosystem product developers to indicate that a product has been shown / demonstrated to meet a minimum set of characteristics and should be interoperable with other OpenPOWER Ready products.  A signed Trademark License Agreement (TMLA) is required for a product to display the mark.   Use of the trademark and the trademark is governed by the TMLA Usage Guidelines.

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Power ISA™ Version 3.0B

The Power Instruction Set Architecture (ISA) Version 3.0B is a specification that describes the architecture used for the IBM POWER9 processor.  It defines the instructions the processors execute.  It is comprised of three books and a set of appendices.

• – Book I, Power ISA User Instruction Set Architecture, covers the base instruction set and related facilities available to the application programmer.
• – Book II, Power ISA Virtual Environment Architecture, defines the storage model and related instructions and facilities available to the application programmer.
• – Book III, Power ISA Operating Environment Architecture, defines the supervisor instructions and related facilities.

 

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The OpenPOWER ISA Compliance Definition defines the test suite requirements to demonstrate OpenPOWER ISA Profile compliance for POWER8 systems.

 

The input to this specification are the following specifications:

1. OpenPOWER Specification: Power Instruction Set Architecture (ISA) – OpenPOWER Profile which describes the categories of the POWER ISA Version 2.07 B that are required in the OpenPOWER processor chip architecture.
2. IBM Power ISA Version 2.07 B

 

The testing of a processor implementation’s compliance against the Power ISA – OpenPOWER Profile ensures that software shown to execute properly on one compliant processor implementation will execute properly on a different also compliant processor implementation. The testing is not intended to show that the processor implementation under test is robust under all possible operating conditions, inputs, or event time interactions. It is intend to show that the processor implementation under test implemented the ISA as specified and the ISA specification was interpreted by the processor developers as intended by the ISA specification author.

 

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.

 

Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.

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The OpenPOWER CAPI 1.0 Accelerator Compliance: Test Specification provides the requirements for a test suite to demonstrate OpenPOWER CAPI 1.0 Accelerator compliance for POWER8™ systems. The input to this specification are the subject of this OpenPOWER CAPI 1.0 Accelerator Compliance: Test Specification document:

1. OpenPOWER Power Service Layer (PSL) to Accelerator Function Unit (AFU) Interface Specification, Revision 1.0 which describes the interface to communicate to the acceleration logic running on the FPGA.
2. OpenPOWER Coherent Accelerator Interface Architecture Version 1 (CAIA V1) Specification   which describes a coherent accelerator interface structure for coherently attaching accelerators to the POWER8 systems using a standard PCIe bus.

 

The OpenPOWER CAPI 1.0 Accelerator Compliance: Test Specification is a Standards Track, Work Group Specification owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.

 

Comments about this document may be submitted to the Compliance Workgroup by emailing to <[email protected]>.

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Eight-port internal 12Gb dual core ROC-based SAS solution for data center, cloud, and performance applications using up to 128 SAS or SATA devices

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ConnectX®-4 Lx EN network interface card, 25GbE dual-port SFP+, PCIe3.0 x8, tall bracket, ROHS R6

 

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ConnectX®-4 EN network interface card, 100GbE, dual-port QSFP28, PCIe3.0 x16, tall bracket, ROHS R6

 

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ConnectX®-3 Pro EN network interface card, 10GbE, dual-port SFP+, PCIe3.0 x8 8GT/s, tall bracket, RoHS R6

 

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ConnectX®-3 EN network interface card, 40/56GbE, dual-port QSFP+, PCIe3.0 x8 8GT/s, tall bracket, RoHS R6

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ConnectX®-4 Lx EN network interface card, 10GbE dual-port SFP+, PCIe3.0 x8, tall bracket, ROHS R6

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Spectrum(TM) based 40GbE, 1U Open Ethernet Switch with MLNX-OS, 16 QSFP28 ports, 2 Power Supplies (AC), short depth, Rangeley CPU, P2C airflow, Rail Kit must be purchased separately, RoHS6

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Spectrum(TM) based 10GbE/100GbE 1U Open Ethernet switch with MLNX-OS, 48 SFP28 ports, 8 QSFP28 ports, 2 power supplies (AC), x86 dual core, Short depth, P2C airflow, Rail Kit, RoHS6

 

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CAPI enabled hardware compression

 

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Broadcom NetXtreme® C-Series Dual Port 25G Cloud-Optimized PCIe Ethernet NIC

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This document describes a Field replaceable unit Support Interface(FSI) suited to service all chips in a computer system via a common serial interface. Key features are ease of use, easy scalability, robustness, and support for virtualization and the tunneling of interrupts and DMA control signals across the interface. FSI is superior to similar industry standard interfaces in these and many other features including speed, distance, data protection, and address range.

FSI is a point to point two wire interface operating in half duplex mode, which is capable of supporting distances of up to 4 meters at up to 166 MHz bus frequency. All operations are fully CRC checked to allow error recovery.
With its versatile architecture, the FSI is suited for a wide range of applications from service access to in-system test.

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Power8 2-socket server system – Open Compute, Open Rack form factor, based upon OCP Barreleye G1 specification.

 

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High-density, scalable, and cost-effective design includes 60 Ultrastar® 3.5-inch drive modules in a 4U storage enclosure and offers 2x2x4-lane SAS 12Gb/s performance, high availability (HA), and hot-swappable components.

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IBM Power ISA™ Version 2.07B

The Power Instruction Set Architecture (ISA) Version 2.07B is a specification that describes the architecture used for the  IBM® POWER8®, IBM® POWER8® with NVIDIA® NVLink™ Technology, the Suzhou Powercore Technology CP1 processor & prior IBM Power Architecture® processors.  It defines the instructions the processors execute. It consists of five books and a set of appendices.

• Book I, Power ISA User Instruction Set Architecture, covers the base instruction set and related facilities available to the application programmer.
• Book II, Power ISA Virtual Environment Architecture, defines the storage model and related instructions and facilities available to the application programmer.
• Book III-S, Power ISA Operating Environment Architecture – Server Environment, defines the supervisor instructions and related facilities used for general purpose implementations.
• Book III-E, Power ISA Operating Environment Architecture – Embedded Environment, defines the supervisor instructions and related facilities used for embedded implementations.
• Book VLE, Power ISA Operating Environment Architecture – Variable Length Encoding (VLE) Instructions Architecture, defines alternative instruction encoding and definitions intended to increase instruction density for very low end implementations.

The Power ISA specification is an important resource for software developers especially compiler and tool chain developers.  Firmware and operating system developers will also find it essential.  The reference link will require an IBMid to access.  If you do not have one please request one as you login.

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2U 2S Power8 Storage Rich Server

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SwitchX®-2 based 40GbE, 1U Open Ethernet Switch with MLNX-OS, 36 QSFP+ ports

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SwitchX®-2 based 48x10Gb and 12x40Gb, 1U Open Ethernet Switch with MLNX-OS

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Spectrum® based 100GbE, 1U Open Ethernet Switch, 32 QSFP28 ports

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SwitchX®-2 based 10GigE, 1U Open Ethernet Switch with MLNX-OS, 64-port SFP+

 

 

 

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SwitchX®-2 based 10GbE/40GbE, 1U

Open Ethernet Switch with MLNX-OS, 12

QSFP+ ports

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Set of open source development tools and runtime libraries which allows users to take leading edge advantage of IBM’s latest POWER hardware features on Linux

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AuvizDNN is an optimized library of functions similar to CuDNN to create deep learning algorithms on FPGA accelerators.

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This architecture specification provides a comprehensive computer system platform-to-software interface definition,combined with minimum system requirements, that enables the development of and software porting to a range of compatible industry-standard computer systems from workstations through servers. These systems are based on the requirements defined in the Power Instruction Set Architecture (ISA) . The definition supports the development of both uni-processor and multi-processor system implementations.

 

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Emulex Gen 6 (16Gb) Fibre Channel HBA

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Emulex Gen 5 (16Gb) Fibre Channel HBA

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Emulex 8Gb Fibre Channel HBA

 

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Emulex 8Gb Fibre Channel HBA

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Emulex Gen 6 (32Gb) Fibre Channel HBA

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Quad-port 8Gbps Fibre Channel Adapter, low profile, PCIe® 2.0 x8

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The PBlaze4 Series is Memblazes’ next generation enterprise SSD designed to deliver consistent level of performance and  reliability for the most demanding data center applications, including database, CDN, Tier1 Caching, Virtualization and Cloud Computing.

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Compiler for Fortran on Linux LE on Power systems

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Compiler for C and C++ on Linux LE on Power systems Free of charge

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Compiler for C and C++ on Linux LE on Power systems

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OpenPower8 based 2-Socket Rack Server

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Ubuntu Leading OS for Cloud & Scaleout computing

 

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The DRAGEN Bio-IT Platform is based on the highly reconfigurable DRAGEN Bio-IT Processor which is integrated on a PCIe card and is available in a pre-configured server that can be seamlessly integrated into customer’s NGS bioinformatics workflows. The platform can be loaded with highly optimized algorithms for many different NGS secondary analysis pipelines such as Whole Genome or Exome, RNAseq, Methylome, Microbiome and Cancer.

 

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Connect-IB® Host Channel Adapter, dual-port QSFP, FDR 56Gb/s, PCIe3.0 x16, tall bracket, RoHS R6

 

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ConnectX®-4 VPI adapter card, EDR IB (100Gb/s) and 100GbE, single port QSFP28, PCIe3.0 x16, tall bracket, ROHS R6

 

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ConnectX®-4 Adapter Card

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NVIDIA-K80-GPU PCIe gen3 x16 GPU Adapter (FC EC4B; CCIN 2CE9)

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NVIDIA® K40 GPU Adapter. PCIe gen3 x16 GPU Adapter (FC EC47; CCIN 2CE8)

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The Emulex® PCIe G3 x8 4×10 4-Port Ethernet SR Optical / SFP+ Cu. This adapter uses Emulex
controller XE201 (in NIC only mode)

 

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The QLogic® 57810 PCIe2 4-Port (2P 10Gb+2P 1GbE) SR/SFP+ Cu +RJ45 Adapter

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The QLogic® 57810 PCIe2 2-port 10GBaseT RJ45 Adapter

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The Broadcom® NetXtreme® BCM 5719 PCIe2 4-port 1GbE Adapter

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The Emulex® PCIe Gen3 4-port (10Gb FCoE and 1GbE) SR&RJ4 – SR and Cu. This adapter uses
Emulex Engine™ XE201 (in NIC+ FCoE converged NIC mode)

 

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The Mellanox® ConnectX-3® Pro PCIe3 2-Port 10 GbE NIC RoCE SR/SFP+ adapter

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The Mellanox® ConnectX-3® PCIe3 2-Port 40 GbE NIC RoCE QSFP+ Adapter

 

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The Mellanox ConnectX®-4 PCIe3 1-port 100Gb EDR IB Adapter x16

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The Mellanox ConnectX®-4 PCIe3 2-port 100Gb EDR IB Adapter x16

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Dual-port Gen 5 (16Gbps) Fibre Channel Adapter, low profile, PCIe® 3.0 x4

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PCIe 2.0 x8 to 8-port SAS/SATA 6 Gbps RAID-On-Chip processor

 

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PCIe 2.0 x8 to 4-port SAS/SATA 6 Gbps RAID-On-Chip processor

 

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PCIe 3.0 x8 to 8-Port 12 Gbps SAS/6 Gbps SATA I/O Controller

 

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PCIe 3.0 x8 to 16-Port 6 Gbps SATA I/O Controller

 

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One-lane PCIe 2.0 to Four-port 6Gbps SATA I/O controller

 

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PCIe 3.0 x8 to 16-Port 12 Gbps SAS/6 Gbps SATA I/O Controller

 

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Two-lane PCIe 2.0 to Four-port 6Gbps SATA I/O controller

 

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PCIe 2.0 x2 to 4-port SATA 6 Gbps RAID controller

 

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PCIe 2.0 x8 to 8-port SAS/SATA 6 Gbps I/O controller

 

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PCIe 2.0 x4 to 4-port SAS/SATA 6 Gbps I/O controller

 

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Dual-port 8Gbps Fibre Channel Adapter, low profile, PCIe® 2.0 x4

 

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The Mellanox Connect-IB® PCIe3 2-port 56Gb FDR IB Adapter x16.

 

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POWER8 Server

 

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POWER8 Server

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POWER8 Server

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POWER8 Server

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POWER8 Server

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2205-L2C, 2205-L2G

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2200-L2C, 2200-L2G

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Xilinx Virtex-7 FPGA accelerator Board

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Chelsio’s T520-SO-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 10 GbE memory free Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

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Chelsio’s T520-BT is built upon the Terminator 5 (T5) High Performance ASIC and is a 10GBase-T 10 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

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Chelsio’s T520-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 10 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

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Chelsio’s T580-SO-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 40 GbE memory free Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

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Chelsio’s T580-LP-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 40 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

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Chelsio’s T580-CR is built upon the Terminator 5 (T5) High Performance ASIC and is a 40 GbE Unified Wire adapter, with PCI Express Gen 3 host bus interface, optimized for cloud computing, HPC, virtualization, storage, and other data center applications

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Xilinx UltraScale FPGA accelerator Board

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FPGA CAPI Accelerator Card

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

6Gb/s SAS/SATA

8 Port Configuration: 2 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

6Gb/s SAS/SATA

16 Port Configuration: 4 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller (Entry-RAID Only)

6Gb/s SAS/SATA

16 Port Configuration: 4 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

Half Length, Full Height

RAID Controller

6Gb/s SAS/SATA

24 Port Configuration: 4 internal mini SAS HD x4 ports, 2 external mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

Half Length, Full Height

RAID Controller

6Gb/s SAS/SATA

24 Port Configuration: 6 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

6Gb/s SAS/SATA

24 Port Configuration: 2 internal mini SAS HD x4 ports, 4 external mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

12Gb/s SAS and 6Gb/s SATA

4 Port Configuration: 1 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

12Gb/s SAS and 6Gb/s SATA

8 Port Configuration: 2 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller

12Gb/s SAS and 6Gb/s SATA

16 Port Configuration: 2 internal mini SAS HD x4 ports, 2 external mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

RAID Controller; Embedded Flash Backup and AFM-700 included

12Gb/s SAS and 6Gb/s SATA

16 Port Configuration: 4 internal mini SAS HD x4 ports

 

SUPPORTED HDD/SSD DEVICES: http://adaptec.pmcs.com/en-us/_common/compatibility/

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PCIe Gen 3.0 x8

MD2 Low Profile

NVM Express NVRAM Drive

Flash-based Backup Unit: SCM-F35 Bulk

Memory Configuration: 4GB Capacity

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PCIe Gen 3.0 x8

MD2 Low Profile

NVM Express NVRAM Drive

Flash-based Backup Unit: SCM-F70 Bulk

Memory Configuration: 8GB Capacity

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PCIe Gen 3.0 x8

MD2 Low Profile

NVM Express NVRAM Drive

Flash-based Backup Unit: SCM-F100 Bulk

Memory Configuration: 16GB Capacity

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Power8 2U2S System

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This IBM® Redbooks® publication focuses on gathering the correct technical information, and laying out simple guidance for optimizing code performance on IBM POWER8® processor-based systems. There is straightforward performance optimization that can be performed with a minimum of effort and without extensive previous experience or in-depth knowledge.

 

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IBM® and Linux® deliver servers, software, and solutions built on the IBM Power Systems™ platform. IBM’s Power servers run industry standard Linux from Red Hat®, SUSE™ and Canonical’s Ubuntu®.  This website is your source for technical assistance with Linux software on Power systems (IBM and OpenPOWER), including forums for questions, libraries of technical resources and tools, references to free cloud access, a database of commonly available packages for Linux on Power, and step-by-step guide to migrating Linux applications.

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The IBM Software Development Kit for Linux on Power (SDK) is a free, Eclipse-based Integrated Development Environment (IDE). The SDK integrates C/C++ source development with the Advance Toolchain, Post-Link Optimization, and classic Linux performance analysis tools, including Oprofile, Perf and Valgrind.

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Step-by-step IBM Developer Portal guide for porting applications from x86 Linux to POWER, including application assessment, port planning and selecting development tools.

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The NVIDIA® CUDA® Toolkit provides a comprehensive development environment for C and C++ developers building GPU-accelerated applications. The CUDA Toolkit includes a compiler for NVIDIA GPUs, math libraries, and tools for debugging and optimizing the performance of your applications. You’ll also find programming guides, user manuals, API reference, and other documentation to help you get started quickly accelerating your application with GPUs.

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BM’s CAPI technology provides a high-performance, coherent processor attach for computation-heavy algorithms on an FPGA. This innovation removes the overhead and complexity of the I/O subsystem, allowing an accelerator to operate as part of an application with a smaller programming investment.  The CAPI Developer Kit is now available through OpenPOWER member Nallatech. Nallatech provides the CAPI FPGA Card, documentation, software, and support required to implement a CAPI solution.

 

For the CAPI Developer Kit, see: www.nallatech.com/capi
For information on CAPI, see: http://www-304.ibm.com/webapp/set2/sas/f/capi/home.html

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The Usage Guidelines outline the authorized uses of OpenPOWER Foundation’s trademarks and logos.  A signed Trademark License Agreement (TMLA) is required to display the OpenPOWER Ready mark(s) as described in the Guidelines.  The TMLA document may be downloaded from OpenPOWER Ready Trademark Agreement.

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The OpenPOWER Foundation set up the OpenPOWER Ready™ program in 2016.   Within the program, developers identify products for use by members of the OpenPOWER ecosystem.    The OpenPOWER Ready mark indicates that a product should work with other OpenPOWER Ready products.  Because of this the OpenPOWER Foundation is suggesting that entities providing such products join the foundation.

The OpenPOWER Ready Definition and Criteria document describes the details of the program.    Since there are several types of products categorized in the document they are listed below.  Because of the differences between the categories of products the criteria varies between them.  Developers will find the categories and criteria described in the document.

OpenPOWER Ready Product Categories

• IO Adapters – storage controllers and network controllers are examples of IO Adapters
• Systems
• CAPI Accelerators – Heterogeneous accelerator attached via a CAPI enabled PCIe Adapter
• Operating Systems
• Applications
• System Support Components

 

Companies and other entities can make a strong statement about their support of the OpenPOWER technology as an alternative to other server solutions by becoming a member of the OpenPOWER Foundation membership.

Interested readers can find information about the OpenPOWER Foundation at the foundation’s website:  https://openpowerfoundation.org/.

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OpenPOWER Ready™ is a mark used by the OpenPOWER Foundation to enable OpenPOWER ecosystem product developers to indicate that a product has been shown / demonstrated to meet a minimum set of characteristics and should be interoperable with other OpenPOWER Ready products.  This document is a template for submitting a request to the OpenPOWER Foundation.  Users should fill out this template and submit the request per the OpenPOWER Ready Definition and Criteria.

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1U single-socket OpenPOWER platform supports up to 1,024GB memory

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2U single-socket OpenPOWER platform supports up to 1,024GB memory

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Ultrastar SN150 Series NVMe PCIe 3.0 x4 Half-Height, Half-Length Card Solid-State Drive (SSD)

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High Density, Ultrastar SN150, PCIe SSD, 1.6TB, solid-state drives

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Official repository for the open source OpenPOWER firmware implementation. Contains repositories for firmware components, along with the build system to produce firmware builds for a large range of existing hardware platforms.

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Little Endian (LE) Linux supporting the 64-bit POWER Instruction Set Architecture (ISA) is a foundational part of the OpenPOWER System software stack and supports the development of OpenPOWER applications including future applications leveraging NVIDIA GPUs. The development community will now benefit from the creation of an open source software community for the development of a new ppc64el port, a Debian GNU/Linux distribution. To view additional information about this porting effort including how to access the repository of binaries and pre-installed images, visit Debian-ppc mailing list on the Debian wiki. To report bugs or other issues related to the Debian ppc64el tool as work begins in this community, developers are encouraged to join the debian-ppc mailing list or use the Debian bug reporting site at Debian bug reporting site.

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xCAT offers open source system management for HPC clusters, RenderFarms, Grids, WebFarms, Online Gaming Infrastructure, Clouds, and Datacenters. It is agile, extensible, and based on years of system administration best practices and experience. Now, xCAT enables you to discover OpenPOWER nodes, management OpenPOWER HW and deploy bare-metal and VMs on the OpenPOWER nodes. xCAT is an Open Source product ready for OpenPOWER.

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DESCRIPTION

The Coherent Accelerator Processor Interface (CAPI) on IBM POWER8 systems is a new means for solution architects to gain system-level performance. CAPI connects a custom acceleration engine to the coherent fabric of the POWER8 chip. The hybrid solution has a simple programming paradigm while delivering performance well beyond today’s I/O attached acceleration engines.

 

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The CAPI Developers Community is intended to enable POWER8 CAPI Developer Kit users to collaborate with other users on usage, issues, questions & to innovate.

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Collection of hardware designs for the SP010 POWER8 reference platform.  This OpenPOWER Development Platform Workgroup Note provides the material used for the design of the Tyan SP010 development system as a reference for developers of OpenPOWER systems based on the IBM Power8TM chipset.

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POWER8 Evaluation System is single socket ATX form factor, BMC based evaluation board. It is designed and will be fulfilled by Tyan Corporation an OpenPOWER Foundation Platinum member. Note that this is an early development system for “Evaluation Purposes Only” and not intended for production use. If you are interested in one or more of these Evaluation systems or boards, please click on the link below.

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Attention OpenPOWER and Open Source developers – Can’t wait for Ubuntu to be generally available on POWER? Site Ox, an IBM MSP Partner, is offering Ubuntu, Debian, CentOS, Fedora, and OpenSUSE Linux operating systems on Power (1 CPU, 2GB memory and 20GB disk) for $2 a day and is having a 2-week free promotion. Visit Siteox.com.

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Quad-port Gen 6 (32Gbps) Fibre Channel Adapter, full-height, PCIe® 3.0 x16

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Dual-port Gen 6 (32Gbps) Fibre Channel Adapter, low profile, PCIe® 3.0 x8

 

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Quad-port Enhanced Gen 5 (16Gbps) Fibre Channel adapter, full-height, PCIe® 3.0 x8

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Dual-port Enhanced Gen 5 (16Gbps) Fibre Channel Adapter, low profile, PCIe® 3.0 x8

 

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The purpose of the OpenPOWER Instruction Set Architecture (ISA) Profile specification is to describe the categories of the POWER ISA Version 2.07 B that are required in the OpenPOWER processor chip architecture.

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The purpose of the I/O Design Architecture, version 2 (IODA2) specification is to describe the chip architecture for key aspects of PCIe® based host bridge (PHB) designs for IBM® POWER8TM systems.

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This document defines the Coherent Accelerator Interface Architecture (CAIA) for the IBM® POWER8® systems. The information contained in this document allows various CAIA-compliant accelerator implementations to meet the needs of a wide variety of systems and applications. Compatibility with the CAIA allows applications and system software to migrate from one implementation to another with minor changes.

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A CAPI based accelerator interfaces to the POWER system through a logic unit called the Power Service Layer (PSL).  The Accelerator Function Unit (AFU) contains the logic that implements the unique acceleration function.  This OpenPOWER Accelerator Workgroup Specification defines the logical interface between the PSL and the AFU.

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