Archive

BM’s CAPI technology provides a high-performance, coherent processor attach for computation-heavy algorithms on an FPGA. This innovation removes the overhead and complexity of the I/O subsystem, allowing an accelerator to operate as part of an application with a smaller programming investment.  The CAPI Developer Kit...

DESCRIPTION The Coherent Accelerator Processor Interface (CAPI) on IBM POWER8 systems is a new means for solution architects to gain system-level performance. CAPI connects a custom acceleration engine to the coherent fabric of the POWER8 chip. The hybrid solution has a simple programming paradigm while delivering...

The CAPI Developers Community is intended to enable POWER8 CAPI Developer Kit users to collaborate with other users on usage, issues, questions & to innovate. ...

This document defines the Coherent Accelerator Interface Architecture (CAIA) for the IBM® POWER8® systems. The information contained in this document allows various CAIA-compliant accelerator implementations to meet the needs of a wide variety of systems and applications. Compatibility with the CAIA allows applications and system...

A CAPI based accelerator interfaces to the POWER system through a logic unit called the Power Service Layer (PSL).  The Accelerator Function Unit (AFU) contains the logic that implements the unique acceleration function.  This OpenPOWER Accelerator Workgroup Specification defines the logical interface between the PSL...