Abstract to be presented at Summit 2016
The Coherent Accelerator Processor Interface (CAPI), a unique feature of the POWER architecture, provides co-processors and I/O devices direct access to the CPU’s coherent memory system. The tight coupling with the host memory allows for eliminating a vast part of the I/O driver overhead which in turn facilitates the offload of even small software routines to hardware accelerators.
We present a CAPI-based FFT accelerator that is integrated into the industry standard FFTW library and works fully transparent to the end user. Calls to the FFTW library are intercepted, analyzed and, if appropriate, dispatched to the FPGA accelerator at run-time. Compared to optimized software on the POWER8 host system, the accelerator delivers >3x serial performance and >15x better energy efficiency. Du to the compliance with the FFTW API, no code changes are required in the application code and also existing tools that are linked against the FFTW shared library can use the accelerator. The FFT accelerator is now available as a public demo on the SuperVessel cloud platform.
Heiner Giefers received his diploma and PhD degrees from the University of Paderborn, Germany in 2006 and 2012, respectively. After receiving his PhD he held a position as technical consultant for FPGA-accelerated high-performance computing at the Paderborn Center for Parallel Computing (PC2). In 2013 he joined the IBM Zurich Research Laboratory where he is working on energy-efficient architectures, reconfigurable computing and hardware-software codesign.