As part of the OpenPower ecosystem, there is a need to define architectural compliance criteria, to ensure compliance of any new design developed over the Power architecture. Relying on many years of experience in hardware verification, our group at IBM Research has developed a methodology for testing architectural compliance. This methodology attempts to catch every type of potential misinterpretation of the architecture. We propose to present this methodology, show how it fundamentally differs from a hardware verification methodology, and demonstrate how it leads to the specification of a compliance testing suite for the Power architecture.
Laurent received his M.A. in computer science from the Technion, Israel in 1999. Since 2000 he has been at IBM Research Haifa, working on development of hardware verification tools. He was a developer of the RuleBase formal verification tool, specializing in assertions and temporal languages, and participated in the IEEE committee for defining the PSL My current focus is on architectural compliance specification and testing.standard. He also developed the DIVER tool for designer-level logic verification.