Jülich Tag Teams With IBM, Nvidia On Data Centric Computing

Industry Coverage

The Power Acceleration and Design Center that has just been launched at the Jülich Supercomputing Center in Munich, Germany, is not just about focusing the system research and software development around IBM’s Power processors and Nvidia’s Tesla GPU accelerators. More importantly, the center is hanging out a shingle and letting organizations in Europe know where to go to get help to solve their peskiest “data centric” application problems.

The center will draw on an existing partnership between Jülich and Nvidia, which was established in 2012, and the long-standing relationship between IBM and the German supercomputing center that saw Jülich deploy multiple generations of Big Blue’s BlueGene massively parallel Power-based systems. Since 2011, IBM and Jülich have been collaborating on future exascale system designs, and Dave Turek, vice president of technical computing and OpenPower at IBM, tells HPCwire that the new center will formalize and enhance the three-way collaboration that the parties have already been engaged in.

“We have a plan, of which this is really just the first step, in getting a variety of skills brought to bear to focus on new code development and accelerating existing codes to take advantage of the architectures that IBM is facilitating with our OpenPower partnership with Nvidia and, over the course of time, with others as well,” explains Turek. Jülich, he says, is at the forefront of research in physics and materials science and does a lot of work in life sciences as well, and the work to accelerate its workloads will have a bearing on similar applications at major supercomputer centers around the globe.

“This is meant to carve up the application domain and really put some muscle behind it to get the kind of acceleration we are hoping to see out of the new architectures,” Turek adds. This is not a once shot deal, and is meant to be a long-term relationship between the three parties.”

Jülich and Nvidia have been working together to build accelerator programming skills at the supercomputing center. IBM’s Research and Development Lab in Böblingen, Germany, will bring its expertise on the Power8 architecture and systems design in general to bear on the collaboration effort, and IBM Research Zurich in Switzerland will add its software expertise to the mix. Turek says that the Zurich center will eventually become a focal point for other Power acceleration and design centers that Big Blue hopes to establish in Europe. IBM’s plan calls for the establishment of similar centers in North America and Asia, and the idea is to put them near existing IBM Research facilities to make collaboration easier. But, in this modern Internet age, physical proximity is not an absolute necessity for good collaboration. As the effort evolves, Turek expects for other members of the OpenPower Foundation community will participate, coupling other kinds of accelerators and storage to Power Systems to reduce latency or increase bandwidth or both.

One of the key future technologies for the collaboration between Nvidia and IBM is the NVLink interconnect, which Nvidia revealed at the GPU Technology Conference back in March. NVLink is a point-to-point interconnect that is a superset of the PCI-Express protocol that allows for multiple lanes to be ganged up to hook multiple GPU accelerators to each other or to link GPUs to CPUs that have NVLink ports added to them. The bandwidth between devices linked by NVLink can be increased by somewhere between a factor of 5X and 12X, according to Nvidia, which plans to have NVLink ready for the “Pascal” family of GPUs sometime around early 2016. The Pascal GPUs will also have unified memory addressing between GPUs and CPUs, which will make programming hybrid machines quite a bit easier. (This unified memory feature was originally expected in the “Maxwell” family of GPUs, but has been pushed out to Pascal chips. This is a very difficult thing to do, and IBM would be the first one to admit it.)

IBM has its own means of tightly coupling accelerators to its Power8 processors, called the Coherent Accelerator Processor Interface (CAPI), which is an overlay on top of the PCI-Express 3.0 bus on the Power8 chip that eliminates a lot of the driver overhead for PCI devices and also allows them to directly link into the memory (main and cache) of the Power8 processor complex. This is something that IBM Research called a “hollow core” as CAPI was being designed and prototyped.

IBM is intent on using both CAPI and NVLink in future Power-based systems, so don’t think of it as an either-or scenario. CAPI is already being used to link FPGA accelerators and flash storage to the Power8 processing complex, and it seems likely that with Mellanox Technologies being a founding member of the OpenPower Foundation, we will see a tightly coupled network interface card that reduces latencies even further than the Remote Direct Memory Access (RDMA) protocol does with InfiniBand.

“The way to think about it is that we are taking a direct attack on latency through CAPI and making a direct attack on bandwidth through NVLink,” explains Turek. “All of these things are really meant to deal with data movement issues, which are part of our data centric systems designs.” The goal with the data centric designs IBM is working on is to eliminate data movement as much as possible and to enable processing on data whether it is at rest in storage or in flight in the network. This is an idea IBM has been playing with for several years, and it will be interesting to see what system architectures it delivers embodying this approach. “Data movement is never going away, but having a dramatically improved highway into the chip, either through NVLink or CAPI, as a vehicle for those circumstances when data movement is required. And of course it brings along coherence, which makes programming a lot easier over the course of time.”

As for the Power8 platforms, IBM is shipping the CAPI interface and the firmware that unlocks it now, and customers who want to pair Power8 processors over plain vanilla PCI-Express 3.0 ports with Tesla GPU coprocessors from Nvidia can also do so. Turek added that he expected that first Nvidia GPUs exploiting CAPI could come to market before the end of 2015 and that the earliest parts from IBM and Nvidia that exploit NVLink could come out around that same time.

“So it is not dramatically that far off into the future, and certainly from the perspective of the design center we are setting up in Germany, which is of course informed on all of these matters, their work will be split across doing real-time enablements and optimizations on conventionally attached GPUs while in the background setting out the planning and other things to get us ready for the availability of these other pathways.”