OpenPOWER CAPI 2.0 Accelerator Compliance: Test Specification

Details

Date Added: February 15, 2018

Revision: 1.0 WG Specification

capi2-compl-thts-1.0

Categories

Level One

  • Developer Resources

Level Two

  • OpenPOWER Documents

Level Three

  • Specifications
  • Hardware Focus

Keywords

CAPI 2.0ComplianceOpenPOWER ReadyOPR

The purpose of the OpenPOWER CAPI 2.0 Accelerator Compliance: Test Specification is to provide the test suite requirements to demonstrate OpenPOWER CAPI 2.0 Accelerator solution compliance for POWER9™ systems. The input to this specification are the following specifications which define the hardware interfaces which are the subject of this OpenPOWER CAPI 2.0 Accelerator Compliance document:

  1. OpenPOWER Power Service Layer (PSL) to Accelerator Function Unit (AFU) Interface CAPI 2.0 Specification, Revision 1.0 which describes the interface to communicate to the acceleration logic running on the FPGA.
  2. OpenPOWER Coherent Accelerator Interface Architecture Version 2 (CAIA 2) Specification which describes a coherent accelerator interface structure for coherently attaching accelerators to the POWER9 systems using a standard PCIe bus.

 

This document is a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.   Comments, questions, etc. can be submitted to the public mailing list for this document at <[email protected]>.