Date Added: May 8, 2020
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- OpenPOWER Documents
- General Architecture
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This is the review draft of theOpenPOWER I/O Design Architecture, version 3 (IODA3) Compliance Test Harness and Test Suite (TH/TS) specification version 1.0-PRD. This document is proposed as a Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. Comments, questions, etc. can be submitted to the public mailing list for this document at [email protected].
The purpose of the OpenPOWER I/O Design Architecture, version 3 (IODA3) Compliance Test Harness and Test Suite (TH/TS) specification is to provide the test suite requirements to be able to demonstrate OpenPOWER I/O Design Architecture, version 3 (IODA3) compliance for POWER9 (TM) systems. It describes the tests required in the test suite and a test harness needed to execute the test suite. It also describes the successful execution of the test suite, including what it means for an optional feature to fail.
The input to this specification is the OpenPOWER I/O Design Architecture, version 3 (IODA3) Specification which describes the chip architecture for key aspects of PCI Express® (PCIe)-based host bridge (PHB) designs for POWER9 systems. This specification defines the PHB hardware and firmware requirements for these functions:
- MMIO Partitionable-Endpoint Number Determination,
- DMA and MSI Partitionable-Endpoint Number Determination,
- Partitionable-Endpoint State and Enhanced Error Handling,
- DMA with No Page Migration,
- DMA with Page Migration,
- DMA with Multilevel TCE Tables,
- DMA Read Sync Register,
- Message-Signalled Interrupt,
- PCIe Configura- tion Space, and
- Partitionable-Endpoint State Table.
**The Public Review for this document completes at close-of-business on June 19, 2020.**