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List of Figures

2.1. Structure Smaller than a Word
2.2. Structure with No Padding
2.3. Structure with Internal Padding
2.4. Structure with Internal and Tail Padding
2.5. Structure with Vector Element and Internal Padding
2.6. Structure with Vector Element and Tail Padding
2.7. Structure with Internal Padding and Vector Element
2.8. Structure with Internal Padding and 128-Bit Integer
2.9. Packed Structure
2.10. Union Allocation
2.11. Simple Bit Field Allocation
2.12. Bit Field Allocation with Boundary Alignment
2.13. Bit Field Allocation with Storage Unit Sharing
2.14. Bit Field Allocation in a Union
2.15. Bit Field Allocation with Unnamed Bit Fields
2.16. Floating-Point Registers as Part of VSRs
2.17. Vector Registers as Part of VSRs
2.18. Stack Frame Organization
2.19. Minimum Stack Frame Allocation with and without Back Chain
2.20. Passing Arguments in GPRs, FPRs, and Memory
2.21. Parameter Passing Definitions
2.22. Passing Homogeneous Floating-Point Aggregates and Integer Parameters in Registers without a Parameter Save Area
2.23. Passing Homogeneous Floating-Point Aggregates and Integer Parameters in Registers without a Parameter Save Area
2.24. Passing Floating-Point Scalars and Homogeneous Floating-Point Aggregates in Registers and Memory
2.25. Passing Floating-Point Scalars and Homogeneous Floating-Point Aggregates in FPRs and GPRs without a Parameter Save Area
2.26. Passing Homogeneous Floating-Point Aggregates in FPRs, GPRs, and Memory with a Parameter Save Area
2.27. Passing Vector Data Types without Parameter Save Area
2.28. Passing Vector Data Types with a Parameter Save Area
2.29. Direct Function Call
2.30. Indirect Function Call (Absolute Medium Model)
2.31. Small-Model Position-Independent Indirect Function Call
2.32. Large-Model Position-Independent Indirect Function Call
2.33. Branch Instruction Model
2.34. Absolute Switch Code (Within) for static modules located in low or high 2 GB of address space
2.35. Absolute Switch Code (Beyond) for static modules beyond the top or bottom 2 GB of the address space
2.36. Position-Independent Switch Code for Small/Medium Models (preferred, with TOC-relative addressing)
2.37. Position-Independent Switch Code for All Models (alternate, with GOT-indirect addressing)
2.38. PIC Code that Avoids the lwa Instruction
2.39. Before Dynamic Stack Allocation
2.40. Example Code to Allocate n Bytes
2.41. After Dynamic Stack Allocation
3.1. Thread Pointer Addressable Memory
3.2. TLS Block Diagram
3.3. Local Exec TLS Model Sequences
4.1. File Image to Process Memory Image Mapping

List of Tables

2.1. Little-Endian Bit and Byte Numbering Example
2.2. Little-Endian Bit and Byte Numbering in Halfwords
2.3. Little-Endian Bit and Byte Numbering in Words
2.4. Little-Endian Bit and Byte Numbering in Doublewords
2.5. Little-Endian Bit and Byte Numbering in Quadwords
2.6. Big-Endian Bit and Byte Numbering Example
2.7. Big-Endian Bit and Byte Numbering in Halfwords
2.8. Big-Endian Bit and Byte Numbering in Words
2.9. Big-Endian Bit and Byte Numbering in Doublewords
2.10. Big-Endian Bit and Byte Numbering in Quadwords
2.11. Scalar Types
2.12. Vector Types
2.13. Decimal Floating-Point Types
2.14. IBM EXTENDED PRECISION Type
2.15. IEEE BINARY 128 QUADRUPLE PRECISION Type
2.16. Bit Field Types
2.17. Little-Endian Bit Numbering for 0x01020304
2.18. Big-Endian Bit Numbering for 0x01020304
2.19. Register Roles
2.20. Floating-Point Register Roles for Binary Floating-Point Types
2.21. Floating-Point Register Roles for Decimal Floating-Point Types
2.22. Vector Register Roles
2.23. Absolute Load and Store Example
2.24. Small Model Position-Independent Load and Store (DSO)
2.25. Medium or Large Model Position-Independent Load and Store (DSO)
2.26. Mappings of Common Registers
2.27. Address Class Codes
3.1. Special Sections
3.2. Relocation Table
3.3. General Dynamic Initial Relocations
3.4. General Dynamic GOT Entry Relocations
3.5. Local Dynamic Initial Relocations
3.6. Local Dynamic GOT Entry Relocations
3.7. Local Dynamic Relocations with Values Loaded
3.8. Initial Exec Initial Relocations
3.9. Initial Exec GOT Entry Relocations
3.10. Local Exec Initial Relocations (Sequence 1)
3.11. Local Exec Initial Relocations (Sequence 2)
3.12. General-Dynamic-to-Initial-Exec Initial Relocations
3.13. General-Dynamic-to-Initial-Exec GOT Entry Relocations
3.14. General-Dynamic-to-Initial-Exec Replacement Initial Relocations
3.15. General-Dynamic-to-Initial-Exec Replacement GOT Entry Relocations
3.16. General-Dynamic-to-Local-Exec Initial Relocations
3.17. General-Dynamic-to-Local-Exec GOT Entry Relocations
3.18. General-Dynamic-to-Local-Exec Replacement Initial Relocations
3.19. Local-Dynamic-to-Local-Exec Initial Relocations
3.20. Local-Dynamic-to-Local-Exec GOT Entry Relocations
3.21. Local-Dynamic-to-Local-Exec Replacement Initial Relocations
3.22. Local-Dynamic-to-Local-Exec Replacement GOT Entry Relocations
3.23. Initial-Exec-to-Local-Exec Initial Relocations
3.24. Initial-Exec-to-Local-Exec GOT Entry Relocations
3.25. Initial-Exec-to-Local-Exec Replacement Initial Relocations
3.26. Initial-Exec-to-Local-Exec X-form Initial Relocations
3.27. Initial-Exec-to-Local-Exec X-form GOT Entry Relocations
3.28. Initial-Exec-to-Local-Exec X-form Replacement Initial Relocations
4.1. Program Header Example
4.2. Memory Segment Mappings
4.3. Registers Specified during Process Initialization
5.1. Predefined Target Architecture Macros
5.2. Predefined Target Data Order Macros
6.1. Endian-Sensitive Operations
6.2. Altivec Memory Access Built-In Functions
6.3. Optional Built-In Memory Access Functions
6.4. Optional Fixed Data Layout Built-In Vector Functions
6.5. Built-In Interfaces for Inserting and Extracting Elements from a Vector
6.6. Optional Built-In Functions
6.7. Altivec Built-In Vector Memory Access Functions (BE Layout in LE Mode)
6.8. Optional Built-In Memory Access Functions (BE Layout in LE Mode)
6.9. Built-In Vector Conversion Functions
6.10. Fortran Vector Data Types
A.1. Format of Prototypes
A.2. Vector Built-In Functions
A.3. Built-in Vector Predicate Functions
A.4. Built-In Vector Operators for Secure Hashing and Finite Field Arithmetic
A.5. Built-In Vector Operators for the Advanced Encryption Standard
A.6. VSCR Management Functions
A.7. Constants Used with vec_test_data_class
A.8. Functions Provided for Compatibility
A.9. Deprecated Power SIMD Interfaces
A.10. Deprecated Predicates
B.1. Binary-Coded Decimal Built-In Functions
B.2. BCD Functions Defined by bcd.h
B.3. BCD Support Functions
B.4. Constants Used with BCD_FORMAT

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